Advanced packaging — stacking and bonding finished silicon rather than printing more transistors on a single die — has become the part of the roadmap where the AI buildout actually gets gated, and it dominated this week's newly published US patent applications. A tight cluster in the June 25, 2026 drop, classified across the H01L packaging subclasses, is directed at the mechanics of direct bonding (also called hybrid bonding, when conductor-to-conductor and dielectric-to-dielectric contacts are formed in the same plane without an intervening adhesive) and at how to build and take apart the temporary stacks the process depends on. The story here is not a company; it is the engineering of getting two surfaces to fuse, and getting a carrier back off again, at the flatness and cleanliness direct bonding demands.

The hero application, "Direct Bonding and Debonding of Carrier" (US20260182477A1), assigned to the Adeia/Xperi bonding group, addresses a problem that sits underneath the whole flow: once you have thinned a device wafer to tens of micrometers and bonded it to a carrier so it can be handled, how do you release that carrier afterward without mechanical force that would crack the fragile die. The disclosed answer is to release it with light. The application describes an intervening structure — a nonconductive bonding layer, a photolysis layer, and an opaque layer stacked together — sandwiched between the semiconductor element and a transparent carrier. The nonconductive layer is directly bonded; the carrier is then decoupled by shining light through the transparent carrier so it reaches and decomposes the photolysis layer.

The method can include decoupling the transparent carrier from the semiconductor element by exposing the photolysis layer to light through the transparent carrier such that the light decomposes the photolysis layer.— DIRECT BONDING AND DEBONDING OF CARRIER, US20260182477A1

Why the carrier, not just the bond, is the hard part

The reason this is worth a patent application is that direct bonding wants two things that fight each other. The bond itself needs near-perfect, particle-free, planarized surfaces, which is why device wafers get thinned on a carrier in the first place. But a carrier you bonded that well is a carrier you now have to remove without prying. The independent claim recites the carrier structure as a transparent carrier, a photolysis layer over it, an opaque layer over that, and a nonconductive layer whose far side is "prepared for direct bonding to a semiconductor element." The dependent claims fill in the materials engineering: the transparent carrier as glass, the photolysis layer as an ultraviolet (UV) photolysis polymer 100 nm to 1 μm thick, and the opaque layer as a thin metal — titanium, 20 nm to 100 nm — with a reflective face toward the photolysis layer. That opaque reflective layer is the tell. It is positioned so the device side never sees the release light: the light is absorbed where the polymer needs to decompose and bounced back off the metal before it can reach and damage the circuits below. The disclosure even covers the post-release geometry, where after debond the opaque layer and a photolysis remnant remain on the device element rather than the carrier.

Bonding with no rinse, and a 3D IC split across tiers

A second application in the cluster, "Direct Bonding Methods and Structures" (US20260182476A1, inventor Uzoh, also from the Adeia/Xperi lineage), is directed at the surface-preparation sequence rather than the carrier. Its single independent claim recites polishing a first bonding layer that carries both a conductive pad and a non-conductive region, performing a last chemical treatment on the polished layer, and then directly bonding pad-to-pad and dielectric-to-dielectric to a second element without an intervening adhesive — with the explicit limitation that "no treatment or rinse is performed on the first bonding layer between performing the last chemical treatment and directly bonding." In hybrid bonding the dielectric surfaces are typically activated chemically so they fuse at low temperature; the disclosed approach is directed to making that final activating chemistry the last thing the surface sees, on the theory that any rinse or handling afterward is a chance to reintroduce the particles or terminations the activation was meant to set. It is a process-order claim, and the order is the invention.

The third hero comes from a different lineage and a different layer of the stack. "3D IC and a Method for Forming a 3D IC" (US20260182475A1), assigned to imec, is directed not at the bond interface but at how to partition the logic across the two device tiers a stack creates. The disclosed 3D IC carries a data-processing circuit whose launch and capture circuits — the latches or flip-flops that clock data in and out — are placed entirely in a first device tier, while the combinational processing stages between them sit in a second tier above, connected by inter-tier interconnects. Several dependent claims push the idea further: within the volume the circuit occupies, the second tier is "absent of launch and capture circuits," each processing stage is "a dedicated combinational stage," and within the overlapping footprint the second tier is "clock-less." Concentrating all the clocked elements and the clock-distribution network in one tier, and leaving the upper tier purely combinational, is a way to keep the power-hungry, timing-critical clock network confined to a single, fully wired layer instead of routing it up and down through the stack.

The method claims tie that partition back to the bonding theme that runs through the whole cluster: the first tier is built on one wafer and the second tier on another, and the two are joined into a wafer stack — in one variant frontside-to-backside, with the first frontside interconnect structure bonded to a backside interconnect structure on the second wafer that also carries backside power. That is a wafer-on-wafer flow, and a wafer-on-wafer flow is exactly what the carrier-release and last-treatment-bonding applications above are built to support. Read together, the three describe complementary pieces of one process: prepare and activate the surface, fuse it, and get the temporary carrier back off with light.

A fourth application, "A Substrate, in Particular a Lead-Frame Substrate" (US20260182473A1, assigned to Nexperia), sits at the more conventional packaging end of the same drop. It is directed to a layered lead-frame substrate alternating materials of higher and lower coefficient of thermal expansion (CTE) with a thermal via connecting the die-mounting layer through to a lower layer — a structure aimed at moving heat out of the package while managing the CTE mismatch that warps a stack as it cycles. It is a reminder that the same week's packaging disclosures span both leading-edge wafer bonding and the thermal-and-mechanical fundamentals of getting a die's heat to the outside world.

None of these is a granted patent; each is a published application disclosing an approach, with the independent claims defining the scope being sought. What the cluster shows is where this week's disclosed engineering effort concentrated: not on the transistor, but on the bond and the stack around it — light-released carriers, rinse-free activation, and tier-partitioned logic. For the claim-by-claim IP view of these bonding filings, chipclaims tracks the hybrid-bonding claim language; for the capacity and capex context behind the advanced-packaging bottleneck, hardwareledger reads the foundry filings.