Sitemap
108 articlesA complete index of every article on this site.
Semiconductors
- A drop of liquid holds the die while the jig lets go
- Doing Two Jobs in One Refresh Window: Micron's Serialized Row-Counter Update
- Recess-Based Pick and Place: Aligning a Whole Population of Dies at Once
- Huawei Application Splits the SRAM Bit Cell Across Two Device Layers
- TSMC Application Confines Anneal Heat to 10 nm of the Wafer Backside
- Two Liners, Two Moduli: Taming Stress in Through-Glass Vias
- Asymmetric Stacks and Backside Contacts: Inside This Week's GAA Transistor Applications
- Intel's Glass-Core Packaging Grant Puts Dies Above and Below the Glass, With the Bridge Buried in a Cavity
- Direct Bonding, Light-Released Carriers, and Tier-Split Logic: What This Week's 3D-IC Applications Disclose
- Quantum Computing Inc. Closes NHanced Semiconductors Acquisition: What the 8-K Discloses About the Advanced-Packaging Deal
- What Hybrid Bonding Is — the Packaging Step That Joins Dies Without Bumps
- What a Chiplet Is — and Why Breaking the Chip Apart Changes the Whole Design Problem
- What High-NA EUV Lithography Is — and Why a Bigger Numerical Aperture Is the Whole Point
- What the Foreign Direct Product Rule Does to Semiconductors — Read From the Rule
- What the CHIPS Act 'National Security Guardrails' Are — Straight From the Final Rule
- What High-Bandwidth Memory Is — and the Exact Threshold That Put It Under Export Control
- What a Gate-All-Around Nanosheet Transistor Is — and Why the Channel Is the Hard Part
- What Backside Power Delivery Actually Does — Read From the Patent Record
- A Reduced RISC-V Core Built for Tsetlin Machine Inference at the Edge
- ExSpike: An FPGA Neuromorphic Design Runs Spiking Networks End-to-End on Events
- Inside the Gate-Separation Problem: What This Week's GAA Nanosheet Applications Disclose
- A Tariff That Starts at Zero: USTR's Section 301 Action on Chinese Semiconductors Sets a 2027 Trigger
- From Presumption of Denial to Case-by-Case: BIS Opens a Conditional Door for H200 Exports to China
- The 2027 Procurement Wall: What the FAR's Proposed Ban on 'Covered Semiconductor Products' Actually Does
- Can an Agentic Flow Cut RTL Power? AUTOGATE Reports 49% on Small Designs, Single Digits at Industrial Scale
- The Other Half of an AI Chip: MIVE Folds Softmax, LayerNorm and RMSNorm Into One Datapath
- Why 3D-Stacked Chips Need a Faster Thermal Solver: Inside CUTh-Solver's 25x Speedup
- Applied Optoelectronics Doubles Its China Credit Line to RMB 500M — A Working-Capital Signal for AI Optics
- Foreign-Trade Zone Filing Eyes Semiconductor Test Equipment Production in Chandler, Arizona
- ITC Finds Section 337 Violation in Semiconductor Devices, Issues Exclusion Order
- U.S. Implements Taiwan Trade-and-Security MOU, Trimming Section 232 Tariffs
- Pentagon Updates Its List of Chinese Military Companies, Raising Stakes for Chip Suppliers
- Commerce Finds Subsidies in China Solar-Cell Review, Plans Partial Rescission
- ITC Opens Section 337 Probe Into NAND and DRAM Imports Over MonolithIC 3D Patents
- What Actually Gates the AI Hardware Buildout: A Synthesis From the Patent Record
- Broadcom's Latest 10-Q: AI Networking and Custom Accelerators Drove the Quarter
- EUV Needs More Than a Scanner: The Resist and the Stage Nobody Credits
- The Mirrors Behind EUV: Why Zeiss and ASML Optics Are a Chokepoint Inside a Chokepoint
- NVIDIA Patents the Data, Not Just the Chip
- The DRAM Cell Is the Real Memory Wall: Reading Samsung's 2026 Grants
- Feeding Power to a 3D Stack: Intel's Composite-Bridge Grant, Decoded
- Scale-Up Interconnect: What CXL, UALink, and NVLink Are Actually Competing Over
- Anatomy of a Chiplet: The Die-to-Die Link Doing the Work
- What Micron's Latest 10-Q Actually Says About HBM Demand Risk
- Backside Power and Stacked Transistors: Reading IBM's 2026 Thicket
- What Broadcom Means by 'XPU': Reading the Custom-Accelerator Definition in the Proxy
- Reading NVIDIA's 2026 10-K: The China Export-Restriction Language That Keeps Reappearing
- Bandwidth Math: How Stacked Memory Feeds the GPU, Read Through the Patents
- Follow the Capex: TSMC's Board Filings Keep Funding Advanced Packaging
- Why Advanced Packaging, Not 2nm, Is Gating the AI Buildout
- AMD's Instinct Lineup in the 10-K: From MI200 to MI350, on CDNA
- Intel 18A in the Filings: RibbonFET, PowerVia, and What the 10-K Actually Claims
- The EUV Pellicle Problem: A Single Membrane Is Quietly Gating Sub-2nm Yield
- Broadcom's AI Story in the 10-K: Custom Accelerators, XPUs, and Networking
- Eliyan's 2025 Patent: Cheaper Chiplet Packaging Without the Interposer
- IBM's 2025 Hybrid Stacked-FET Patent: Two Transistors, One Footprint
- Broadcom Defines 'AI Revenue' in an 8-K - and the Definition Is the Story
- Apple's 2025 Die-to-Die Patent: High Bandwidth, Less Package Area
- IBM's 2025 'HBM Cube' Application and the Next Memory Geometry
- IBM's 2025 Stacked-FET SRAM Patent: Cache in the Vertical Dimension
- Kepler Computing's 2025 Patent: DRAM Under the Processor
- XPUs as a Risk Factor: How Broadcom's 2025 10-Q Frames Custom AI Silicon
- ASML's High-NA EUV: What the 20-F Calls the TWINSCAN EXE Platform
- AMD's 2024 Backside-Power Application and the Move Below the Wafer
- Samsung's 2024 Patent on Parallel Error Correction in Memory
- TSMC's 2024 Patent: A Voltage Regulator Inside the 3D Stack
- From Application to Grant: Intel's 2024 Sparse-Systolic AI Patent Issues
- What Is HBM, Really? Start With How Micron Defines It in Its Own Filing
- An Additional Licensing Requirement: NVIDIA's 2024 10-Q Tightens the China Disclosure
- Micron's 2024 Centralized Error-Correction Patent
- Intel's 2024 Flipped-HBM Application: Turning the Stack Over for Heat
- MI300 Enters the Record: Reading AMD's 2024 10-K Data Center GPU Line
- Adeia's 2024 Patent: Stacking ICs With Orthogonal Interconnect Layers
- Celestial AI's 2023 Optical Multi-Die Interconnect Bridge
- Broadcom/Avago's 2023 Copper-Bonded Memory-Stack Application
- Marvell's 2023 Silicon-Photonics Patent: Light as the Interconnect
- IBM's 2023 Nanosheet Inner-Spacer Patent: The Tiny Wall That Matters
- IBM's 2023 Asymmetric-Gate Nanosheet Patent
- Samsung's 2023 Stacked-Memory Patent and the Vertical Address Map
- The China Line in NVIDIA's 2023 10-K: A100 and H100 Now Named in Export Rules
- Where NVIDIA's China Risk Factor Began: The FY2023 10-K
- Reading ASML's 2023 20-F: Why the Lithography Chokepoint Files as a Foreign Issuer
- IBM's 2023 Nanosheet-Airgap Patent: Cutting Capacitance With Nothing
- Intel's 2022 Composite-Bridge Patent: Wiring Chiplets Without an Interposer
- Micron's 2022 NAND Physical-Unclonable-Function Patent
- Arm's 2022 Backside Power-Rail Patent: The Architecture, Granted
- Intel's Sparse-Matrix Systolic-Array Patents and the AI-Math Thicket
- After Xilinx: How AMD's First Post-Close 10-Q Describes Its New Portfolio
- Apple's 2022 High-Density 3D Interconnect Patent
- TSMC's 2022 Patent on Catching the Tin: EUV's Debris Problem
- IDM 2.0 in Three Parts: How Intel's 2022 Annual Report Defines the Strategy
- Announced vs Filed: When Intel First Put RibbonFET in a 10-K
- Xilinx's 2021 Multi-Rank HBM Patent and the Capacity Lever
- Intel Puts 'World-Class Foundry Business' in Writing: Reading the 2021 10-Q
- Arm's 2021 Buried-Metal Patent and the Road to Backside Power
- TSMC's 2021 EUV Light-Source Patent and the Throughput Problem
- Samsung's 2021 HBM Patent: Putting Logic Inside the Memory System
- Why TSMC Files a 20-F, Not a 10-K - and What That Annual Report Records
- TSMC's 2021 GAA Grant: Gate-All-Around and Planar on One Die
- Front-to-Back Bonding: TSMC's 2021 TSV Application for 3D Stacking
- Micron's 2020 Grant on GPU-HBM Integration Through a Silicon Interposer
- HBM Shows Up in Micron's 2020 10-K - as One Product Among Many
- GlobalFoundries' 2020 EUV Mask Patent and the Reflective-Optics Problem
- Multi-Threshold Gate-All-Around: What IBM Claimed in 2020
- Anatomy of a Nanosheet: Reading Tessera's 2020 Transistor Grant
- The Stacked DRAM Patent Rambus Filed Before HBM Was Mainstream
- Apple's 2020 Patent on Mixing High- and Low-Bandwidth Memory
- Reading NVIDIA's 2020 10-K: Why Gaming, Not Data Center, Still Leads the Story