The application US20240321702A1 (published September 26, 2024; Advanced Micro Devices, Inc.; CPC H01L 23/49822 substrate power/ground, H01L 23/3675 thermal, H01L 24/05 bond pads, H01L 25/0652 die assembly) describes backside power. The H01L 23/49822 power-substrate code plus the assembly codes signal this is about delivering power through packaging and the die backside.
The payoff for a power-hungry accelerator is direct. AI GPUs draw enormous current, and front-side power networks waste area and suffer voltage droop under that load. Moving power delivery to the backside cuts the resistance of the power path - less droop, more stable voltage at high current - while handing the congested front side back to signal routing.
Note the thermal code (H01L 23/3675) in the classification. Backside power and heat removal interact: the underside is also where you often want to extract heat, so routing power there is entangled with thermal design. AMD's filing touching both is consistent with a high-power accelerator context.
This is an application, so read it as direction and priority rather than a granted claim. The signal is that AMD - not just the IP licensors and IDMs - is now filing its own backside-power IP, which tells you the technique is moving into mainstream high-performance product design.
For the node-watch reader, the arc is clear across the years: backside power went from buried critical nets (Arm, 2021) to a full architecture (Arm, 2022) to research-IDM device integration (IBM, 2024) to accelerator-designer filings (AMD, 2024). The technique is shipping-adjacent now, and the patent record traces the whole climb.