Apple's chip advantage is often framed as architecture, but a large part of it is packaging: how the dies are stacked, wired, and integrated. The 2022 grant is a window into that side of the strategy - a claim on high-density 3D interconnect.
The grant US11309246B2 (issued April 19, 2022; Apple Inc.; CPC H01L 23/5286 through-via interconnect structure, H01L 23/5383 and H01L 23/5386 redistribution/interconnect layers, H01L 25/0652 die assembly) claims a high-density 3D interconnect configuration. The cluster of interconnect-structure CPC codes tells you the novelty is in the wiring geometry, not a new transistor.
Density is the whole game in 3D. Two dies are easy to connect with a few wires; the value is in connecting them with thousands at fine pitch, so the stack behaves like one chip rather than two chips with a bottleneck between them. A 'high density' interconnect configuration is a claim on achieving exactly that.
Apple designs the silicon but uses foundry and packaging partners to build it, which means its packaging IP is about specifying and owning the configuration even when others manufacture it. A high-density 3D interconnect grant protects the architecture regardless of whose assembly line runs it.
Set beside Intel's composite-bridge and TSMC's interposer-and-front-to-back work, this rounds out the 2022 advanced-packaging picture: every serious silicon player was filing on how to stack and wire dies densely, because that is where system-level performance was increasingly won.
For the reader, the durable point is that a 'chip' from a vertically integrated designer is now a package of dies, and the interconnect configuration is as much intellectual property as the cores. Apple's 2022 grant stakes a claim on the 3D wiring that makes its multi-die parts cohere.