Apple's chip advantage is often framed as architecture, but a large part of it is packaging: how the dies are stacked, wired, and integrated. The 2022 grant is a window into that side of the strategy - a claim on high-density 3D interconnect.

The grant US11309246B2 (issued April 19, 2022; Apple Inc.; CPC H01L 23/5286 through-via interconnect structure, H01L 23/5383 and H01L 23/5386 redistribution/interconnect layers, H01L 25/0652 die assembly) claims a high-density 3D interconnect configuration. The cluster of interconnect-structure CPC codes tells you the novelty is in the wiring geometry, not a new transistor.

“Electronic package structures and systems are described in which a 3D interconnect structure is integrated into a package redistribution layer and/or chiplet for power and signal delivery to a die.”— U.S. Patent No. 11,309,246 source

Density is the whole game in 3D. Two dies are easy to connect with a few wires; the value is in connecting them with thousands at fine pitch, so the stack behaves like one chip rather than two chips with a bottleneck between them. A 'high density' interconnect configuration is a claim on achieving exactly that.

Read the independent claim and the structure becomes concrete. Claim 1 describes a redistribution layer (RDL) with a die coupled to it, the RDL itself carrying a 3D interconnect structure for power and signal delivery, and a chiplet mounted on the opposite side of the RDL - positioned, in the claim's own words, “substantially directly underneath the low performance logic.” That last detail is the heart of the disclosure: the die is partitioned into high-performance logic (CPU, GPU, engines) and low-performance logic, and the chiplet is tucked under the cooler, lower-power region. Per the specification, this is deliberate - aligning the interconnect and chiplet under a high-power-density zone “may possibly result in degraded SoC performance,” because that is where the heat and current crowding live. The patent puts numbers on the partition: high-performance logic running 1-10 Watts/mm² against low-performance logic at or below 0.5 Watts/mm².

The mechanism for the density claim is routing direction. The specification contrasts a conventional side-by-side 2D layout, where metal lines run laterally and the die-to-die gap, seal-ring spacing, and peripheral blockage all eat I/O density, against a configuration where the 3D interconnect routes “primarily vertically.” That vertical routing, the disclosure claims, improves I/O density roughly 1.5 to 2× over the 2D case while freeing the die's periphery - the patent notes the SoC gains edge availability on three sides instead of two for high-speed and general-purpose I/O. Shorter vertical links also cut line length (from hundreds or thousands of microns down to roughly 100-200 microns in one example), lowering capacitance, cross-talk, and the driver resistance needed, which the patent ties directly to lower power and latency.

The dependent claims flesh out the power-delivery side. The 3D interconnect is built from “power bars” - wide conductive lines sitting directly underneath grouped contact pads, sized for small IR drop and electromigration margin - feeding Vdd and Vss through a power mesh plane. The chiplet is not just routing: the claims contemplate it carrying an integrated passive device, a power management unit, or a power mesh plane of its own, with backside metal and even a low-dropout or switched-capacitor voltage regulator in some embodiments. Apple is claiming, in other words, a way to push power and signals up to the die from below while reclaiming the lateral area that flat packages waste.

Apple designs the silicon but uses foundry and packaging partners to build it, which means its packaging IP is about specifying and owning the configuration even when others manufacture it. A high-density 3D interconnect grant protects the architecture regardless of whose assembly line runs it - and notably, the disclosure stresses that the approach avoids needing a through-silicon-via interposer, keeping the structure to an organic package with embedded or surface-mounted chiplets.

Set beside Intel's composite-bridge and TSMC's interposer-and-front-to-back work, this rounds out the 2022 advanced-packaging picture: every serious silicon player was filing on how to stack and wire dies densely, because that is where system-level performance was increasingly won.

The specification also works through the second-order problem the structure creates. Tucking a chiplet under the die casts a “shadow” over the circuit board beneath, blocking power-delivery-network area for the whole system. The patent's answer is stacked chiplets: instead of one wide chiplet, two smaller stacked chiplets (built by micro-bump, wafer-on-wafer, or chip-on-wafer) shrink that shadow, freeing board area for additional power bumps. The disclosure lists concrete side benefits of the smaller stacked parts - reduced warpage (keeping the chiplet's Z-height under the solder-ball height), more attach options such as self-aligned solder instead of thermo-compression bonding, finer bump pitch because less solder is needed, and smaller electrostatic-discharge structures that cut pad capacitance. Several embodiments add a through-silicon via from a Vdd or Vss mesh plane down to a backside metal layer on the chiplet, with a backside bump connecting it to the board to strengthen power delivery further.

Even the wiring materials are specified. The redistribution lines and 3D interconnects are formed from copper, titanium, nickel, gold, or combinations, by plating or sputtering followed by etching, with passivation layers of oxide or polyimide between metal levels; the power bars are stacked across metal layers using landed or unlanded vias. The patent reports an example contact-pad array of 64 signal, Vdd, and Vss pads at pad pitches of 10-30 microns - the kind of fine pitch that the vertical 3D routing is meant to enable. It is a complete recipe for trading lateral routing for vertical routing without losing power integrity.

For the reader, the durable point is that a 'chip' from a vertically integrated designer is now a package of dies, and the interconnect configuration is as much intellectual property as the cores. Apple's 2022 grant stakes a claim on the 3D wiring - power bars, vertical routing, stacked chiplets under the cool logic, and backside power - that makes its multi-die parts cohere.