There is a tension at the heart of chiplet design: bandwidth between dies usually costs package area, because more bandwidth means more wires means more space. Apple's 2025 grant claims breaking that tie - high die-to-die bandwidth while actually reducing the package area the interconnect consumes.
The grant US12368137B2, "High bandwidth die to die interconnect with package area reduction" (issued July 22, 2025; Apple Inc.; CPC H01L 25/0657 stacked-die assembly, H01L 24/16 bumps, H01L 24/24/32 bonding, H01L 25/18 multi-chip) claims that combination. The title states the trade-off it resolves outright.
Why is area so precious? Package area is finite and expensive, and in a part with multiple chiplets, every square millimeter the interconnect uses is area not available for compute or memory, or is added cost. An interconnect that delivers the same bandwidth in less area directly improves the system's density and economics.
The how is where the claim lives - some combination of routing geometry, bonding, and stacking (note the H01L 25/18 multi-chip and H01L 24 bonding codes) that packs the connections more efficiently. This is the same area-efficiency instinct as Intel's composite bridge, evolved another generation.
Apple's recurring appearance in advanced-packaging IP - 3D interconnect in 2022, this D2D-area work in 2025 - reflects a company whose performance edge increasingly comes from integration. Apple designs systems of dies, and owning the interconnect IP that makes them dense is part of that edge.
For the reader, the anatomy point is that the figure of merit for a chiplet interconnect is bandwidth per unit area, and the IP race is to push that ratio up. Apple's 2025 grant is a claim on doing so - more bytes per second across the same or less silicon real estate.