There is a tension at the heart of chiplet design: bandwidth between dies usually costs package area, because more bandwidth means more wires means more space. Apple's 2025 grant claims breaking that tie - high die-to-die bandwidth while actually reducing the package area the interconnect consumes.

The grant US12368137B2, "High bandwidth die to die interconnect with package area reduction" (issued July 22, 2025; Apple Inc.; CPC H01L 25/0657 stacked-die assembly, H01L 24/16 bumps, H01L 24/24/32 bonding, H01L 25/18 multi-chip) claims that combination. The title states the trade-off it resolves outright.

“Package structure with folded die arrangements and methods of fabrication are described. In an embodiment, a package structure includes a first die and vertical interposer side-by-side.”— U.S. Patent No. 12,368,137 source

Why is area so precious? Package area is finite and expensive, and in a part with multiple chiplets, every square millimeter the interconnect uses is area not available for compute or memory, or is added cost. An interconnect that delivers the same bandwidth in less area directly improves the system's density and economics.

The mechanism the patent claims is a “folded die” arrangement, and the independent claim spells out its parts. A first die sits side-by-side with a vertical interposer on the first side of a wiring layer; a second die is mounted face-down on the second side of that vertical interposer, spanning over the first die; and a local interposer sits on the opposite side of the wiring layer, electrically tying the first die to the vertical interposer. The vertical interposer, per the specification, provides the vertical interconnection while the local interposer provides the lateral routing - together completing an electrical path from the first die, through the wiring layer and local interposer, back up through the vertical interposer, to the second die. By folding the second die up and over the first rather than laying both flat, the package collapses two dies' worth of footprint toward one.

The disclosure is explicit about why this beats the alternatives. The summary frames folded die structures as a way to “simultaneously achieve both high bandwidth die-to-die interconnects and package footprint (area) reduction.” Against a fan-out RDL or 2.5D side-by-side interposer layout, the stacked fold reduces footprint; against a full 3D face-to-face stack, it claims significant cost savings, because the expensive through-silicon-via interconnections that 3D bonding relies on are largely avoided. This is the area-versus-cost-versus-bandwidth triangle that every chiplet packager negotiates, and Apple's claim is a particular route through it.

The dependent claims map the intended use directly onto Apple-style silicon. The first die is claimed as a CPU or GPU core; the second die can be a memory core or an RF core; and the two together “comprise split logic” - one IP block (say CPU) on one die, another (say GPU or memory-application processor) on the other, optionally fabricated on different process nodes. The patent notes the first die's transistors may be built on a smaller node than the second die's, exactly the heterogeneous-node mixing that motivates die splitting in the first place. A mechanical chiplet, often silicon for thermal-expansion matching, fills the remaining area over the larger first die for mechanical and thermal stability, and the structure can be finished as a package-on-package with a DRAM or NAND chip mounted on top.

The bonding detail is where the bandwidth lives. The specification describes the vertical interposer being attached to the daughter die by hybrid bonding to reach a terminal pitch below 15 microns, or by micro-bumps for a pitch under 40 microns - fine enough to carry the thousands of parallel die-to-die signals a high-bandwidth link needs. Reaching that pitch in a folded, area-reduced structure rather than across a sprawling interposer is the resolved trade-off the title advertises.

Why is area so precious? Package area is finite and expensive, and in a part with multiple chiplets, every square millimeter the interconnect uses is area not available for compute or memory, or is added cost. An interconnect that delivers the same bandwidth in less area directly improves the system's density and economics. This is the same area-efficiency instinct as Intel's composite bridge, evolved another generation.

Apple's recurring appearance in advanced-packaging IP - 3D interconnect in 2022, this D2D-area work in 2025 - reflects a company whose performance edge increasingly comes from integration. Apple designs systems of dies, and owning the interconnect IP that makes them dense is part of that edge.

The fabrication flow in the specification shows how the fold is assembled, and the sequence is itself part of the disclosure. The daughter (second) die and a mechanical chiplet are placed face-up on a carrier substrate, often within rows of pre-plated conductive pillars. The vertical interposer is then bonded to the daughter die - by hybrid bonding (metal-to-metal and oxide-to-oxide) for the sub-15-micron pitch, or by micro-bumps for the sub-40-micron pitch. The larger first die is stacked face-up on top, secured with adhesive and resting partly on the mechanical chiplet, which is made of silicon for thermal-expansion matching and partial mechanical support. The whole assembly is encapsulated in a first molding compound and planarized to expose terminals; a wiring layer is patterned across the first die and vertical interposer; then the local interposer is mounted face-down on the other side, a second molding compound encapsulates it, and a second wiring layer with landing pads and solder bumps finishes the structure for board mounting.

The geometry claims pin down the area savings. Claim 11 has the first die occupying a larger area than the second die; claim 12 has the second die larger than both interposers; claim 13 has the second die at least partially overlapping both the vertical interposer and the first die. By stacking the daughter die up over the parent and using a thin local interposer (which, per the specification, carries terminals on only one face and serves purely lateral routing), the package reclaims the footprint a side-by-side 2.5D layout would have spent. The patent even offers the final form factors: a package-on-package with a DRAM or NAND chip wire-bonded on top, or a flip-chip ball-grid-array package bonded to a substrate with underfill - the folded core dropped into mainstream package types.

For the reader, the anatomy point is that the figure of merit for a chiplet interconnect is bandwidth per unit area, and the IP race is to push that ratio up. Apple's 2025 grant is a claim on doing so by folding one die over another - vertical interposer for the up-and-over signals, local interposer for the lateral ones - more bytes per second across the same or less silicon real estate.