The instinct in memory design is to want everything fast, but bandwidth is expensive in power, area, and cost. Apple's 2020 grant takes the opposite, pragmatic stance: combine a small high-bandwidth memory with a large high-density (but lower-bandwidth) memory and let the system route data to whichever fits.
The grant US10573368B2 (issued February 25, 2020; Apple Inc.; CPC G11C 11/4023 DRAM operation, G11C 5/063 stacked packaging, H01L 25/0657 stacked-die assembly) claims a memory system that explicitly mixes the two regimes. The title is unusually descriptive: high-density/low-bandwidth paired with low-density/high-bandwidth.
The bandwidth math is the design rationale. A high-bandwidth pool delivers GB/s but costs you per gigabyte; a high-density pool gives you capacity cheaply but cannot feed the processor as fast. Pairing them lets the hot working set live in the fast pool while the cold bulk sits in the dense pool - you pay for bandwidth only where it earns its keep.
This is the same logic that now drives AI memory hierarchies: a limited HBM tier in front of larger, cheaper memory. Apple was claiming the structural idea in a 2020-granted patent, before the AI accelerator market made memory tiering a headline constraint.
The packaging CPC codes (H01L 25/0657 stacked die) signal this is not purely an architectural abstraction - the claim contemplates physical integration of the two memory types, not just two separate sticks on a board. That is what makes it a hardware patent rather than a software caching scheme.
For the memory reader, the durable point is that bandwidth and capacity are different resources with different costs, and the smart designs spend on each separately. Apple's 2020 grant is an early, explicit claim on doing exactly that.