A year after the buried-metal-for-critical-nets work, Arm's IP on the underside of the chip matures into a full architecture. Where the earlier grant moved a few timing-critical wires below the transistors, the 2022 grant claims an entire power-delivery rail on the backside.
The grant US11443777B2, "Backside power rail architecture" (issued September 13, 2022; Arm Limited; CPC G11C 5/14 power-supply arrangements for memory, G11C 8/08 word-line/control), claims a backside power-rail structure aimed at memory devices. The G11C classifications anchor it in memory power distribution specifically.
Why move power to the back at all? On the front side, fat power rails compete with fine signal wires, and the power network's metal forces compromises on routing and density. Put power delivery on the backside and the front side is freed for signal - cells get denser and the power network can be lower-resistance, cutting the voltage droop that limits clock speed.
Naming matters here. The industry markets backside power under various brand names, but the patent calls it what it is - a backside power-rail architecture - and ties it to concrete memory power-supply classifications. That is the chipdocket discipline: trace the marketing term to the granted claim.
Read in sequence with Arm's 2021 buried-metal grant and the parallel Tokyo Electron and IBM filings, this completes a clear thicket arc: the architectural idea broadening from individual nets to a complete power rail, with multiple players staking adjacent claims as manufacturing matured.
For the logic reader, the point is that backside power delivery is a granted, architected, owned thing - not a vague roadmap promise. Arm's 2022 grant is a load-bearing piece of that ownership, filed and examined before the feature shipped in volume.