Backside power delivery - routing the power network on the underside of the wafer - is now a marquee feature of leading-edge nodes. But the enabling idea, putting metal beneath the devices, shows up in the patent record earlier and in pieces. Arm's 2021 buried-metal grant is one such piece.
The grant US11271567B1 (issued March 8, 2022; filed and developed in 2020-2021; Arm Limited; CPC H03K 19/1774 and H03K 19/1776, programmable/critical logic interconnect) claims a buried-metal technique specifically for critical signal nets - the timing-sensitive wires you most want out of the congested front-side stack.
Why bury metal at all? The front side of an advanced chip is a traffic jam: signal routing, power rails, and vias all compete for the same layers. Moving some of that wiring beneath the transistors relieves congestion. Arm's twist is to do it for critical nets - the ones whose delay sets the clock - where freeing routing space buys the most.
This sits at the front edge of a thicket that later fills out with full backside power-delivery networks from Arm, IBM, Intel, and Tokyo Electron. Reading it in sequence, you see an architectural idea (metal below devices) start narrow (critical nets) and broaden (whole power networks) as the manufacturing caught up.
Arm's role is worth noting: an architecture and physical-IP licensor, not a fab. Arm filing buried-metal IP means the building blocks of backside routing were being defined at the IP-licensing layer, to be delivered to whichever foundry implemented them - again, the IP precedes the shipping node.
For the logic reader, the rule holds: backside power did not appear fully formed in a 2024 keynote. It was assembled from grants like this one, where the unglamorous problem - where do you put the wires - was being solved years ahead, net by net.