The interposer is both the enabler and the bottleneck of advanced packaging: it gives chiplets dense connections, but it is expensive silicon and its capacity is a gating constraint on the whole AI buildout. Eliyan's 2025 grant claims a way to get chiplet integration with less reliance on it.
The grant US12494469B1, "Low cost solution for 2.5D and 3D packaging using USR chiplets" (issued December 9, 2025; Eliyan Corp.; CPC H01L 25/18 multi-chip assembly, H01L 23/5384 interconnect, H01L 24/06/14/20 bonding) claims exactly that low-cost approach built on ultra-short-reach (USR) chiplet links.
The idea behind USR is that if the die-to-die link is engineered to drive a very short, well-controlled distance at high speed, you may not need interposer-grade routing density everywhere - you can use cheaper substrate technology for much of the connection. Less expensive silicon interposer means lower cost and less exposure to interposer capacity shortages.
Eliyan is a specialist in die-to-die interconnect IP, and the chipdocket record already includes its bandwidth-balancing D2D work. This 2025 grant extends that franchise from the link itself to the packaging strategy around it - selling not just the wire but the cheaper way to assemble the system.
The chokepoint framing is the point. CoWoS-style interposer capacity has been the single most-cited gating factor in AI hardware. Any credible approach that reduces dependence on scarce interposer supply is strategically valuable, and a granted claim on a low-cost USR-based alternative is a stake in that ground.
For the reader, the takeaway is that the packaging bottleneck is itself under attack by IP. Eliyan's 2025 grant is a bet that high-quality short-reach links can substitute for some interposer routing - relieving the chokepoint that announced AI roadmaps keep running into.