SRAM (static random-access memory) has stopped shrinking at the rate the logic around it does, and the reason is geometric: the six transistors of a bit cell sit shoulder to shoulder in the substrate, so the cell's area is the sum of six footprints, and the transistors cannot all be made smaller without giving up the drive current the cell depends on. An application Huawei Technologies Co., Ltd. published Thursday — US20260206566A1, "STATIC RANDOM-ACCESS MEMORY ARRAY, MEMORY, AND ELECTRONIC DEVICE" — proposes to stop solving that in two dimensions and split the bit cell across the vertical stack instead.

The structure is the whole of it. In a conventional cell, every transistor is built in the FEOL (front-end-of-line) device layer — the transistor-forming steps performed in the silicon substrate itself. This application keeps the PFETs (P-type field-effect transistors) there and moves the NFETs (N-type field-effect transistors) up into a BEOL (back-end-of-line) device layer, the levels ordinarily reserved for the wiring stack built above the substrate. Independent claim 1 recites a semiconductor substrate, a front-end-of-line device layer disposed in it, a back-end-of-line device layer disposed on the front-end-of-line layer, and memory cells in which the PFET is formed in the former and the NFET in the latter. Dependent claim 2 is what licenses the word "stacked": it adds that the NFET's orthographic projection on the substrate at least partially overlaps the PFET's, meaning the two genuinely sit above one another rather than merely occupying different levels. The record carries 20 claims.

Why the roles were assigned that way

The split is not arbitrary, and the application's SUMMARY explains the reasoning. The transistors in a 6T cell do not have equal jobs: per the record's own account of the prior art, the pull-down transistor carries the highest turn-on performance requirement, the access transistor the next, and the pull-up transistor the lowest. Since size drives turn-on performance, shrinking all six uniformly degrades the ones that can least afford it — which is why, in the applicant's framing, "the sizes of the transistors are strictly limited, and the sizes cannot be further reduced with miniaturization of a process node." So the filing assigns the NFET, used as the pull-down transistor with the higher demand, to the back-end-of-line process, and leaves the PFET, used as the pull-up with the lower demand, in the front-end-of-line layer. The proposition is that at a given process node you hold pull-down performance where it needs to be and recover area by taking the cell into the third dimension. The claimed payoff is stated in the SUMMARY, and it is stated oddly:

Through use of the process structure, a vertical projection region of a memory cell can be reduced to 2/N of that of an existing structure (all transistors of a memory cell are made by using the front-end-of-line process). The memory density can be significantly improved.— STATIC RANDOM-ACCESS MEMORY ARRAY, MEMORY, AND ELECTRONIC DEVICE, US20260206566A1

The "2/N" is exactly as the record prints it, and N is not defined in that passage. It is quoted here unrepaired because repairing it would be inventing a number the applicant did not commit to. What can be said about the figure is what it is: an applicant's assertion inside a summary section, not a measurement, not a benchmark, and not something the document supports with fabrication data. The same caution applies to the whole record. This is an A1 publication — an application laid open, not a granted patent, not examined to allowance. It contains no yield data, no measured results, and no evidence that anything described in it has been built. Publication establishes that Huawei filed.

A detail on cell types is worth getting right, because the record is not internally uniform. The abstract offers the 6T and 8T memory cell as examples; the SUMMARY additionally mentions a 3T cell. The abstract's language is the narrower of the two. Neither passage names a process node — the document says "process node" generically throughout and never attaches a number to it — and neither names a foundry, a product, or a competing approach. The filing is a continuation of PCT/CN2024/097127, filed 2024-06-03, claiming priority to CN 202311183082.3, filed 2023-09-13. Six inventors are named: Weiliang Jing, Shihui Yin, Xiaoxuan Zhao, Ying Wu, Zhengbo Wang, and Heng Liao. The record establishes their inventorship and nothing further about any of them.

One silicon record in a drop of 52

The context here is unusual, and it is the opposite of a cluster. Huawei placed 52 publications in Thursday's drop — 49 under HUAWEI TECHNOLOGIES CO., LTD., two under Huawei Digital Power Technologies Co., Ltd., and one under Huawei Cloud Computing Technologies Co., Ltd., which are distinct assignee strings and are counted separately here. Across all 52, US20260206566A1 is the only memory, SRAM, transistor, or semiconductor-device record. There is no related-art cohort to read it against. The rest of the day's drop is dominated by wireless and 5G communications, antennas, handset interfaces, foldable hinges, displays, wearables, and neural-network software.

The nearest-adjacent records in that drop are adjacent only in the loosest sense, and none is related art to an SRAM filing. US20260205142A1 describes a forward-error-correction encoder with finite-field modules, framed as a chip — the closest thing in the drop to a digital-logic hardware record, which is not close. US20260206396A1 covers a display drive backplane bonded to an epitaxial wafer: wafer-bonding process work, but aimed at microLED display rather than logic or memory. US20260202631A1 is chip packaging in the optical domain. US20260203175A1 uses the word "memory," but it means system RAM shared across datacenter hosts for virtual-machine failover — a different sense of the word entirely. US20260203563A1 and US20260203582A1 are neural-network software, on quantization and training schedules respectively.

That isolation is the honest observation to draw, and it is more interesting than a manufactured theme would be. A company whose Thursday output runs to antennas, hinges, and training schedules published exactly one record about the inside of a transistor stack, and that record proposes rearranging the SRAM bit cell along the vertical axis. What the document supports is that claim: PFETs below in the front-end-of-line layer, NFETs above in the back-end-of-line layer, footprints overlapping, offered as a route past the transistor-sizing limit that has capped SRAM density. What happens to it next is a matter for examination.