High-bandwidth memory today is a stack - DRAM dies piled vertically with through-silicon vias. IBM's 2025 application points at a next geometry: not just a stack but a cube, a more fully three-dimensional memory block. The title is literal - "High Bandwidth Memory Cube."
The application US20250220926A1 (published July 3, 2025; inventors including John Knickerbocker and Mukta Ghate Farooq of IBM; CPC H10B 80/00 memory-device assembly, H01L 25/0652 die assembly, H01L 25/18 multi-chip, H01L 2225 stacked-die interconnect) describes a high-bandwidth memory cube. The H10B 80/00 memory-assembly code with the multi-chip stacking codes frames it as a 3D memory structure.
Why move from stack to cube? A stack grows bandwidth and capacity in one dimension - height - and eventually thermal and interconnect limits cap how tall you can go. A more cubic geometry distributes the dies and their connections in more directions, which in principle offers more interconnect surface and capacity without simply building an ever-taller, hotter tower.
The named inventors are a signal. Knickerbocker and Farooq are veteran IBM packaging researchers, and their presence marks this as serious 3D-integration research rather than a speculative sketch. IBM Research has a long history of prototyping memory geometries ahead of the industry.
It is an application, so the disciplined reading is direction and priority, not an enforceable claim. What it tells you is where leading-edge memory-packaging thought is heading in 2025 - past the conventional stack toward denser 3D arrangements - and who is staking early ground there.
For the bandwidth reader, the takeaway is that memory geometry is still evolving. The stack was not the final form; IBM's 2025 HBM-cube application is evidence that the industry is already exploring the next shape, chasing more bandwidth and capacity by using all three dimensions more fully.