Gate-all-around is not the end of the transistor roadmap. The next move many expect is the stacked FET - or complementary FET (CFET) - which puts one transistor directly on top of another, fitting a full CMOS pair into the footprint that used to hold one device. IBM's 2025 grant claims a hybrid version of that.
The grant US12471364B2, "Hybrid stacked field effect transistors" (issued November 11, 2025; International Business Machines Corporation; CPC H10D 84/856 and H10D 30/6735 - note the new H10D device-classification scheme replacing parts of the old H01L 29 codes) claims a hybrid stacked-FET structure. The H10D 84/856 code reflects the updated classification for these advanced stacked devices.
The density argument is the whole motivation. If you can stack the n-type transistor over the p-type instead of placing them side by side, a CMOS cell shrinks dramatically - you reclaim the lateral area the second device used to occupy. That is the kind of step-function scaling the industry needs once lateral shrinking stalls.
'Hybrid' is the operative qualifier and where the claim's scope sits. It signals a stacked structure that mixes elements - potentially different channel types, materials, or integration schemes between the upper and lower devices - rather than a uniform stack. The specific hybridization is the claimed invention.
The classification change itself is worth flagging. Seeing H10D codes (the newer device-classification scheme) instead of the familiar H01L 29 codes marks how recent this device generation is - the taxonomy is updating to describe architectures like CFET that did not exist in volume when the old codes were written.
For the claim reader, the lesson is to read what is actually stacked and how. IBM's 2025 hybrid stacked-FET grant is a claim on the post-GAA architecture, and - consistent with IBM's whole nanosheet portfolio - it is the research IDM staking the foundational device IP years before the foundries ship it.