There is an old trick in interconnect design: the lowest-capacitance dielectric is no dielectric at all - air, or better, vacuum. IBM's 2023 nanosheet grant brings that trick inside the transistor, placing inner air gaps exactly where parasitic capacitance does the most damage.
The grant US11557651B2 (issued January 17, 2023; INTERNATIONAL BUSINESS MACHINES CORPORATION; CPC H01L 29/068 / H01L 29/0653 channel region, H01L 29/66545 GAA fabrication, H01L 29/78696 nanosheet device) claims nanosheet transistors with inner air gaps. The combination of nanosheet and air-gap CPC codes pins down what the claim covers: a GAA device with engineered voids.
Why does capacitance matter so much in a nanosheet? Stacking channels and wrapping the gate around them packs conductors very close together, and close conductors form capacitors whether you want them or not. That parasitic capacitance must be charged and discharged every switch, burning power and adding delay. Replacing solid dielectric with an air gap slashes it.
The hard part - and where the claim earns its scope - is forming a controlled void inside a structure you are simultaneously trying to build precisely. You need the gap exactly between the right surfaces, stable through subsequent processing, without collapsing the delicate nanosheet stack. The fabrication detail is the invention.
This is classic process-integration IP from IBM Research, the same lineage as its multi-Vt and leakage-control nanosheet grants. Read together, they show a research IDM systematically attacking each loss mechanism in the GAA device - threshold control, leakage, and now parasitic capacitance.
For the claim-focused reader, the discipline is to note what is actually claimed: a nanosheet transistor with inner air gaps, not 'air gaps in general.' The competitive value is in the specific structure and how it is formed - which is exactly the kind of limitation that decides scope and design-arounds.