Symmetry is the default assumption in transistor design, but defaults exist to be broken when breaking them buys something. IBM's 2023 grant claims a nanosheet transistor with an asymmetric gate stack - intentionally different gate construction on the source side versus the drain side.
The grant US11652156B2 (issued May 16, 2023; International Business Machines Corporation; CPC H01L 29/6656 GAA fabrication, H01L 29/42376 gate-electrode structure, H01L 29/66553 nanosheet process, H01L 29/785) claims the asymmetric gate stack. The H01L 29/42376 gate-electrode code is where the asymmetry lives in the classification.
What does asymmetry buy? In a transistor, the source and drain ends face different electrical conditions - the drain typically sees higher fields. A gate engineered asymmetrically can be optimized for those differing conditions: better control where you need it, lower capacitance or leakage where you can afford it. One device, two tailored ends.
This is the kind of fine-grained device tuning that defines mature GAA process development. Once the basic nanosheet works, the gains come from these refinements - asymmetric gates, inner air gaps, work-function tuning - each squeezing a bit more performance or efficiency from the same architecture.
It also illustrates how broad a single architecture's patent space is. 'Nanosheet transistor' is not one patent; it is a thicket of grants on every adjustable parameter. IBM's asymmetric-gate claim is one node in that thicket, distinct from and complementary to its symmetric-device IP.
For the claim reader, the discipline is to read the limitation precisely: the claim covers an asymmetric gate stack, and the competitive question is what asymmetry, formed how. That is where scope and design-around space are decided - not in the abstract idea of asymmetry but in the specific claimed structure.