In a finFET, isolating the gate from the source/drain is relatively easy. In a nanosheet, where the gate wraps fully around stacked channels, you need a tiny dielectric wall - an inner spacer - tucked into the gaps between the sheets at the source/drain ends. It sounds minor; it is decisive for device quality. IBM's 2023 grant claims it.
The grant US11764265B2 (issued September 19, 2023; International Business Machines Corporation; CPC H01L 29/0665 source/drain region, H01L 29/0847, H01L 29/1608, H01L 29/6653 GAA process, H01L 29/66545) claims a nanosheet transistor with inner spacers. The H01L 29/0665 and H01L 29/6653 codes together pin down the source/drain-to-gate isolation context.
Why does this little wall matter so much? Without a good inner spacer, the gate sits too close to the source/drain, creating parasitic capacitance and risking leakage paths - the same loss mechanisms IBM attacks elsewhere with air gaps and asymmetric gates. The inner spacer is the first line of defense, built into the most delicate part of the structure.
Formation is the whole difficulty. The spacer must be created in nanometer-scale cavities between sheets, during a process flow that is etching and depositing all around it, without damaging the channels. The claim's value lies in a manufacturable way to put the right dielectric in exactly the right tiny place.
Across the 2023 nanosheet record - inner air gaps, asymmetric gates, inner spacers - IBM is methodically claiming each micro-feature of the GAA transistor. The inner spacer is among the most fundamental, because almost every nanosheet device needs one, which makes IP here broadly relevant.
For the claim reader, the lesson is altitude: the most consequential transistor IP can be about a structure measured in nanometers and described in a single clause. IBM's 2023 inner-spacer grant claims one such structure - small, ubiquitous, and load-bearing for the whole GAA transition.