Cache is precious and stubbornly large. SRAM, the memory used for processor caches, has been scaling more slowly than logic for years, so cache eats an ever-bigger share of die area. IBM's 2025 grant attacks this by building the SRAM cell from stacked FETs, moving the cell into the vertical dimension.
The grant US12328859B2, "Stacked FET SRAM" (issued June 10, 2025; International Business Machines Corporation; CPC H10B 10/125 - the static-RAM device classification in the newer H10B scheme) claims a stacked-FET SRAM cell. The dedicated H10B 10/125 SRAM code makes the application explicit: this is a memory-cell structure, not a logic-only device.
An SRAM cell is itself a little circuit of transistors - classically six. If you can stack those transistors vertically instead of laying them all out flat, the cell shrinks in area, and a smaller cell means more cache bits per square millimeter. Given how poorly flat SRAM has scaled, that vertical reclaim is genuinely valuable.
This is the stacked-FET architecture applied to memory rather than logic, and the pairing with IBM's hybrid stacked-FET logic grant the same year is deliberate. A coherent stacked-FET technology has to handle both the logic cells and the SRAM cells, and IBM is filing on both faces of it.
The stakes are concrete for AI and high-performance chips, which devote huge area to cache to keep data near the compute. Any technique that packs more SRAM into less area directly buys more on-chip cache - which, like the broader memory-near-compute theme, helps feed hungry processors.
For the reader, the anatomy lesson is that even cache is going 3D. IBM's 2025 stacked-FET SRAM grant claims building static memory cells upward, attacking the SRAM-scaling wall the same way logic is attacking the density wall - by using the vertical dimension that flat layouts left on the table.