Cache is precious and stubbornly large. SRAM, the memory used for processor caches, has been scaling more slowly than logic for years, so cache eats an ever-bigger share of die area. IBM's 2025 grant attacks this by building the SRAM cell from stacked FETs, moving the cell into the vertical dimension.

The grant US12328859B2, "Stacked FET SRAM" (issued June 10, 2025; International Business Machines Corporation; CPC H10B 10/125 - the static-RAM device classification in the newer H10B scheme) claims a stacked-FET SRAM cell. The dedicated H10B 10/125 SRAM code makes the application explicit: this is a memory-cell structure, not a logic-only device.

“A semiconductor device is provided that includes at least one stacked FET device including two top transistors stacked over a single bottom transistor.”— U.S. Patent No. 12,328,859 source

An SRAM cell is itself a little circuit of transistors - classically six. If you can stack those transistors vertically instead of laying them all out flat, the cell shrinks in area, and a smaller cell means more cache bits per square millimeter. Given how poorly flat SRAM has scaled, that vertical reclaim is genuinely valuable.

The independent claim describes an unusual stack: not the symmetric two-over-two of a generic stacked FET, but “two top transistors stacked above a single bottom transistor.” That 2:1 arrangement is the structural signature of this patent. To carve it out of a single fabricated stack, the claim relies on three distinct gate-cut structures: a full gate cut at the periphery that isolates one device area from the next, a top gate cut that separates the two upper transistors from each other, and a bottom gate cut placed laterally beside the single bottom transistor, beneath one of the top devices. Read together, those cuts let IBM build two top transistors and one bottom transistor in the same vertical column and then electrically partition them into the right circuit nodes - the precise, manufacturable recipe for a 6T cell folded into the third dimension.

The dependent claims confirm the destination. Claim 9 states the two top transistors and the single bottom transistor are components of an SRAM cell; claim 12 pairs two such stacked devices, side by side, to “provide a 6T SRAM” - the canonical six-transistor cell, now assembled from two stacked-FET columns instead of six planar transistors spread across the wafer. Each transistor is a gate-all-around nanosheet device: claim 2 has every transistor wrapping at least one channel nanosheet, with a dielectric nanosheet separating the top and bottom stacks (claim 3). The patent also specifies complementary doping - claim 18 makes the bottom transistor one conductivity type and the top transistors the other (p-type bottom with n-type top, or the reverse), exactly the n/p mix a CMOS storage cell needs.

The cross-couple wiring - the feedback that makes SRAM hold its state - is where the vertical structure earns its complexity. The claims describe shared gate structures with both frontside and backside gate contacts, plus backside and frontside cross-couple contact structures, and shared source/drain contacts reaching between a top transistor and the bottom transistor. Routing that feedback through both faces of the stack is what lets a folded cell still behave like a flat six-transistor latch.

Crucially, the patent leans on backside power. Claim 10 places a frontside Vss rail above the two top transistors and a backside Vdd supply beneath the single bottom transistor, and claims 16-17 add a backside power rail embedded in interconnect dielectric and a full backside power delivery network underneath. Stacked-FET SRAM and backside power are designed to work together: feeding the cell from below frees the front side for signal routing and helps make the dense vertical cell wireable at all.

This is the stacked-FET architecture applied to memory rather than logic, and the pairing with IBM's hybrid stacked-FET logic grant the same year is deliberate. A coherent stacked-FET technology has to handle both the logic cells and the SRAM cells, and IBM is filing on both faces of it - here, down to the gate-cut sequence that yields the 2:1 stack.

The stakes are concrete for AI and high-performance chips, which devote huge area to cache to keep data near the compute. Any technique that packs more SRAM into less area directly buys more on-chip cache - which, like the broader memory-near-compute theme, helps feed hungry processors.

The integration claims show IBM thinking about the cell as part of a full process flow, not an isolated curiosity. Claim 13 stacks the conventional build above the device - a middle-of-the-line dielectric over the two top transistors, a back-end-of-the-line interconnect structure on top of that, and a carrier wafer above the BEOL - which is the wafer-bonding-and-flip sequence that backside-power processes use to expose the wafer's underside. Claim 14 adds a dielectric layer beneath the stacked device, claim 15 makes the backside gate-cut's bottom surface coplanar with that dielectric, and claims 16-17 then build the backside power rail and full backside power delivery network underneath. Read in order, the claims trace the manufacturing arc: build the 2:1 nanosheet stack, cut it into transistors, wire the front side, bond a carrier and flip, then construct power from the back. The SRAM cell is co-designed with the backside-power and nanosheet platform rather than retrofitted onto it.

Claim 11 also shows how the array tiles. A second stacked-FET device sits laterally adjacent to the first in the same device area, with its own top gate cut separating its two upper transistors and its own bottom gate cut beside its bottom transistor - and claim 12 declares that this pair “provides a 6T SRAM.” So the canonical six-transistor cell is realized as two adjacent three-transistor columns, the full gate cut at the periphery isolating each cell from its neighbors. That is the layout discipline that turns a single clever device into a manufacturable cache array.

For the reader, the anatomy lesson is that even cache is going 3D. IBM's 2025 stacked-FET SRAM grant claims building static memory cells upward - two top transistors over one bottom, partitioned by three gate cuts, fed by backside power, and tiled two columns to a 6T cell - attacking the SRAM-scaling wall the same way logic is attacking the density wall: by using the vertical dimension that flat layouts left on the table.