Gate-all-around (GAA) transistors — stacked horizontal semiconductor sheets fully wrapped by the gate — are the device every leading-edge logic maker is building at the 2nm-class node. The default way to build a CMOS pair is symmetric: the n-channel and p-channel devices share the same stack height, the same number of sheets, and the same channel material, because that is the cheapest thing to fabricate. A large group of applications published in this week's drop and assigned to Intel (INTC), classified under CPC H10D 84/856 and neighboring transistor subclasses, is directed at breaking that symmetry on purpose — and at solving the wiring problem that follows once you do.

The hero application, "Asymmetric Stacks of NMOS and PMOS Transistors in a Hybrid CMOS Architecture" (US20260190475A1), describes a first transistor and a second transistor on a base layer, each a stack of gate-wrapped channel regions, where the two stacks are not coplanar and, in some embodiments, hold a different number of channel sheets. The point of the asymmetry is stated in the dependent claims: one channel is silicon and the other is one of germanium, silicon-germanium, or germanium-tin; one gate carries a p-type work-function metal and the other an n-type. In other words, the application is directed at pairing a silicon NMOS device with a high-mobility germanium-family PMOS device, at different heights, with different sheet counts — a hybrid CMOS cell in which each polarity gets the material and the drive strength it actually wants.

An apparatus provides NMOS and PMOS transistors having asymmetric stacks. The apparatus includes a first transistor and a second transistor on a base layer. ... The first channel regions are not coplanar with the second channel regions. In some scenarios, the number of first channel regions in the first transistor is unequal to the number of second channel regions in the second transistor.— ASYMMETRIC STACKS OF NMOS AND PMOS TRANSISTORS IN A HYBRID CMOS ARCHITECTURE, US20260190475A1

Why asymmetry is worth the process cost

Electron mobility and hole mobility do not live in the same material. Silicon is a good electron transporter and a mediocre hole transporter; germanium and germanium-rich silicon-germanium invert that ranking. A symmetric nanosheet stack forces one compromise material and one compromise sheet count across both devices, which leaves the weaker polarity — usually the p-channel — dragging the cell. The disclosed structure lets the fabricator build the n-device out of silicon and the p-device out of a germanium-family channel, and it lets the two stacks differ in height so the sheet count on each side can be set for balanced drive. The method claims describe growing a stack of two interleaved semiconductor materials and then selectively removing sheets of one material from one device and the other material from the neighbor — a way to fabricate two dissimilar channels from a single starting superlattice.

That places the filing on the same trajectory as the industry's move past uniform nanosheets. GAA/RibbonFET-class devices were the first step; independently tuned n and p channels, and eventually vertically stacked complementary FETs, are the direction the state of the art is pointed. This application does not claim a stacked CFET, but its asymmetric, mixed-material, non-coplanar pair is a recognizable waypoint on that road — an attempt to squeeze per-device optimization out of the nanoribbon platform before the geometry itself changes.

Getting power to a wrapped transistor

The second, larger half of the drop addresses a problem that GAA scaling created rather than solved: once the gate wraps the channel on all sides and the cell shrinks, there is no frontside room left to both signal and power the device. The disclosed answer across the cluster is backside wiring. "Backside Contacts for Improved Source/Drain Connection" (US20260190418A1) is directed at a conductive contact that reaches up into the source or drain region from beneath, with a dielectric liner separating it from the surrounding backside metallization, and it describes a variant where a backside contact meets a frontside contact inside the same source/drain region. "Self-Aligned Backside Contacts Made Using Dielectric Plugs" (US20260190424A1) discloses forming sacrificial dielectric plugs beneath the source/drain during frontside processing, then exposing and replacing them from the backside so the contact lands self-aligned — the alignment margin being exactly what gets scarce at tight pitch.

Isolation follows the contacts to the backside. "Dielectric Trench Plugs Insulating Transistor Source/Drain Material from Backside Metallization" (US20260190442A1) is directed at a plug that keeps the backside power/interconnect metal from shorting into the source/drain it is supposed to route around, while "Backside Fin Isolation Structures Between Semiconductor Devices" (US20260190445A1) describes cutting the device-to-device isolation trench from the backside, leaving an inverse-tapered profile that a frontside etch could not produce. Read together, the contact and isolation filings sketch a full backside-power integration flow — the layer Intel has publicly tied to its leading-edge node.

A third strand of the cluster works inside the transistor. "Memorized Source-Drain Strain in Gate-All-Around Transistors" (US20260190467A1) discloses using sacrificial materials in the source/drain trenches to lock strain into the nanoribbon channels before those materials are removed — strain being the classic lever for carrier mobility. "Selective Dipole Layers for Nanowire Field Effect Transistors" (US20260190473A1) is directed at placing a lanthanum-containing layer on the n-type nanowires but not the p-type ones, so the two share a gate stack while landing different threshold behavior, and "Multi-Threshold Gate Dielectric Patterning Scheme Using Individualized Gate Tubs" (US20260190460A1) describes a dielectric wall that divides wrapped channels into separate "tubs" so adjacent transistors can carry different gate-dielectric stacks and therefore different threshold voltages.

None of these is a granted patent; each is a published application disclosing an approach, with its independent claims defining the scope being sought. Taken as a set, the drop is less about the nanoribbon channel as a headline than about everything pressed up against it — the asymmetric material pairing, the backside contact and its liner, the isolation cut, the strain memory, the per-device threshold. That is where leading-edge logic actually gets gated: not in announcing a device, but in integrating one that yields at pitch. For the claim-by-claim scope of these applications, chipclaims reads the independent claims; for what the filing cadence suggests about Intel's foundry direction, hardwareledger reads the same drop as a business signal.