There are two ways to give chiplets the dense, short connections they need. One is a full silicon interposer spanning the whole package - expensive and capacity-constrained. The other is a small bridge die buried in the substrate just where two chiplets meet. Intel's 2022 grant claims a composite version of the latter.
The grant US11521932B2 (issued December 6, 2022; Intel Corporation; CPC H01L 23/5384 interconnect structure, H01L 25/0652 stacked/side-by-side dies, H01L 24/16 flip-chip bumps) claims composite-bridge die-to-die interconnects. This is the IP family behind Intel's EMIB (embedded multi-die interconnect bridge) approach.
The economic argument is straightforward. A silicon interposer must be as large as the dies it spans, and large silicon is costly and yield-limited. A bridge only has to be as big as the connection region between two chiplets - a tiny fraction of the area - so you get interposer-class wiring density only where you need it.
"Composite" is the operative word in the claim. It points to a bridge built from more than one material or layer system, engineered to handle the bumps, dielectric, and routing of a high-density die-to-die link. The competitive scope lives in exactly how that composite stack is constructed.
This is the architectural counterpoint to TSMC's interposer-centric (CoWoS) packaging: same goal - feed chiplets dense connections - different structure. Reading both, you see the advanced-packaging field splitting into the interposer camp and the embedded-bridge camp, each with its own patent thicket.
For the packaging reader, the takeaway is that 'advanced packaging' is not one technique. Intel's 2022 composite-bridge grant is a bet that you can get most of the interposer's benefit at a fraction of the area cost - a bet that shapes how AI accelerators get assembled when interposer capacity is the bottleneck.