There are two ways to give chiplets the dense, short connections they need. One is a full silicon interposer spanning the whole package - expensive and capacity-constrained. The other is a small bridge die buried in the substrate just where two chiplets meet. Intel's 2022 grant claims a composite version of the latter.

The grant US11521932B2 (issued December 6, 2022; Intel Corporation; CPC H01L 23/5384 interconnect structure, H01L 25/0652 stacked/side-by-side dies, H01L 24/16 flip-chip bumps) claims composite-bridge die-to-die interconnects. This is the IP family behind Intel's EMIB (embedded multi-die interconnect bridge) approach.

“Disclosed embodiments include composite-bridge die-to-die interconnects that are on a die side of an integrated-circuit package substrate and that contacts two IC dice and a passive device that is in a molding material, where the molding material also contacts the two IC dice.”— U.S. Patent No. 11,521,932 source

The economic argument is straightforward. A silicon interposer must be as large as the dies it spans, and large silicon is costly and yield-limited. A bridge only has to be as big as the connection region between two chiplets - a tiny fraction of the area - so you get interposer-class wiring density only where you need it.

"Composite" is the operative word in the claim, and reading claim 1 shows what it composes. The composite-bridge interconnect contacts dedicated “composite-bridge bond pads” on each of two IC dice while deliberately exposing a separate set of “package-connect bond pads” on those same dice - so the bridge owns the die-to-die signaling, and ordinary package power and I/O still flow straight down to the substrate through the exposed pads. What makes it composite is the third element sitting in the structure: a passive device located laterally between the two dice and contacting the bridge, all of it - dice, passive, and bridge - encased in a common molding material. The bridge is not just a slab of routing silicon; it is a routing element integrated with an embedded passive component, which is the part the claim guards.

The dependent claims enumerate what that integration can carry. Claim 2 puts a first lateral interconnect in the bridge coupling die one to the passive device, and a second coupling die two to the passive device. Claim 3 adds a “die-to-die trace” that bypasses the passive entirely and connects the two dice directly - so the bridge simultaneously offers a routed-through-passive path and a clean point-to-point path. Claim 4 layers in a conductive shield whose footprint projects onto the bond pads and the passive device, the kind of structure you add to manage cross-talk and return current on a high-density link. Claim 11 reframes the whole thing as a package: a substrate with a die side and a land side, the two dice and bridge on the die side, package-connect bumps landing the dice to the substrate, and the bridge plus passive molded together above.

The passive-device elaborations are where the “composite” idea is pushed hardest. The claims contemplate multiple passives between the dice (claim 15), stacked passives - a first upper passive with a first lower passive directly below it, both contacting the bridge (claims 16-17, 19) - and even a bottom passive on the land side coupled back to one of the dice (claim 10). The patent is staking out a bridge that doubles as a substrate for embedded decoupling and similar passives right at the die-to-die boundary, exactly where signal integrity and power delivery are tightest. Further claims attach chiplets to the IC dice through through-silicon vias (claims 13-14) and even name end applications - a printed wiring board with a chipset, in a mobile computing system or a drone (claims 20-21).

The economic argument is straightforward. A silicon interposer must be as large as the dies it spans, and large silicon is costly and yield-limited. A bridge only has to be as big as the connection region between two chiplets - a tiny fraction of the area - so you get interposer-class wiring density only where you need it, and here you get embedded passives in the bargain.

This is the architectural counterpoint to TSMC's interposer-centric (CoWoS) packaging: same goal - feed chiplets dense connections - different structure. Reading both, you see the advanced-packaging field splitting into the interposer camp and the embedded-bridge camp, each with its own patent thicket.

The breadth of the passive-device claims is what makes this more than an incremental bridge patent. Claim 18 scales the structure out to four IC dice - a third and fourth die adjacent to the original two, with a third passive device between the first and fourth dice, all tied to the composite bridge - so the same architecture extends from a two-chiplet link to a multi-chiplet cluster sharing embedded passives. Stacking passives vertically (an upper passive with a lower passive beneath, both contacting the bridge) and placing a bottom passive on the substrate's land side coupled back up to a die means the bridge becomes a hub for power-conditioning components distributed in three dimensions around the die-to-die boundary. For an AI accelerator that needs tight decoupling right where compute chiplets exchange data, that co-location is a real electrical advantage, and the claims reserve a wide range of ways to achieve it.

The molding material is the quiet structural constant across every claim. In claim 1 it “contacts the first and subsequent IC dice, the passive device and the composite-bridge die-to-die interconnect” - a single encapsulant binding dice, bridge, and passives into one rigid body on the die side of the substrate. That shared molding is what lets the bridge be embedded and planar with the package rather than a separate component bolted on, and it is why the abstract emphasizes the molding contacting both dice. Combined with the package-connect bumps carrying power and I/O straight to the substrate, the result is a self-contained die-side module: dense routing and passives where the chiplets meet, conventional package escape everywhere else.

For the packaging reader, the takeaway is that 'advanced packaging' is not one technique. Intel's 2022 composite-bridge grant is a bet that you can get most of the interposer's benefit - plus integrated passives, a direct die-to-die trace, and a path to four-die clusters - at a fraction of the area cost, a bet that shapes how AI accelerators get assembled when interposer capacity is the bottleneck.