HBM's bandwidth comes from stacking DRAM dies tightly, and tightly stacked dies trap heat. In an AI accelerator package, the HBM sits next to a power-hungry compute die, and getting heat out of the memory stack becomes a real constraint. Intel's application addresses it by flipping the stack's orientation.

The application US20230081139A1 (published March 2023, in the 2024 development window; Intel Corporation; CPC H01L 23/367 thermal/heat dissipation, H01L 25/0652 die assembly, H01L 25/18 multi-chip, H01L 23/5384/5386 interconnect) describes an IC package with a flipped HBM device. The H01L 23/367 thermal-dissipation code is the tell that this is a heat-path optimization.

“An example microelectronic assembly includes a substrate, a bridge die over the substrate, and a die stack between the substrate and the bridge die, the die stack including a logic die and at least one memory die, where the logic die is between the at least one memory die and the bridge die.”— U.S. Patent Application 2023/0081139 A1 source

Orientation matters thermally because the heat source and the heat sink are in fixed places. By flipping the HBM, you can shorten the thermal path from the hottest layers to whatever removes the heat - a heat spreader or cold plate - rather than forcing heat to travel up through the whole stack. Geometry becomes cooling.

Read claim 1 and the “flip” becomes a specific stacking order. A bridge die sits over the substrate; a die stack sits between the substrate and that bridge die; and within the stack, the logic die is sandwiched between the memory die and the bridge die. In a conventional HBM stack the logic base die sits at the bottom, against the substrate, with the DRAM layers piled on top. Here the order is inverted so the logic die - the hot one, doing the I/O and bandwidth work - faces the bridge rather than being buried under the memory. Claim 9 makes the thermal intent explicit: an integrated heat spreader is added with the logic die placed between the spreader and the memory dies, putting the hottest layer closest to the heat-removal path. Reorienting the device is, literally, moving the heat source toward the sink.

The independent claims add a second structural move to make that fit: recessing the stack into the package. Claim 10 describes an HBM die stack whose end die attaches to a portion of the package substrate, with the bridge electrically connected to the base die - and claim 12 places at least part of the stack in a cavity provided in the substrate's surface, the end die attaching inside that cavity. Sinking the memory stack into the substrate lowers the overall package profile and helps the flipped logic die line up with the bridge and the cooling path above. Claim 2 generalizes the recess; claim 3 adds adhesive between the stack and the cavity to hold it.

The bridge is doing real work here, not just routing. Claim 10 specifies the bridge carries both a power channel and an I/O signal channel, and claim 11 differentiates them physically: the power interconnect structures have a larger diameter than the I/O signal interconnects. That sizing split reflects the two jobs a bridge to a flipped HBM must handle - delivering current through fat power vias while carrying many fine high-speed signal lines - and claim 5 separately notes the bridge-to-logic interconnects use a finer pitch than the bridge-to-substrate interconnects. The bridge can be silicon, glass, mold, an organic, a ceramic, or a high-dielectric material (claim 7).

There is always a trade. Flipping the device may complicate the electrical connections - which way the interface faces, how it bonds to the substrate or interposer - so the value of the claim is in arranging the flip while keeping the high-bandwidth interface workable. The fabrication method in claims 18-20 shows the sequence the inventors landed on: attach part of the HBM stack (including its end die) to the substrate surface, optionally into a pre-formed cavity, then provide the bridge structure over the base die with power and I/O interconnects. Thermal and electrical co-design is the hard part, and the method claim is essentially the recipe for doing the flip without losing the link.

This is a different lever on the same constraint that drives backside power and on-stack regulation: as integration densifies, power and heat become the binding limits. Intel attacking HBM thermals by reorienting the stack - logic-up, recessed into the substrate, bridge-fed - fits the broader pattern of packaging-level problem-solving.

The application also keeps the flipped HBM compatible with a heterogeneous neighbor, which is the realistic use case in an accelerator. Claims 13-14 add a separate IC assembly over a second portion of the package substrate - a third die with a fourth die stacked on it - and place at least part of that assembly between the bridge and the package, so the same bridge structure can span both the flipped memory stack and an adjacent logic-on-logic stack. Claims 4, 8, and 15 introduce a secondary substrate between the primary substrate and the assembly, listing the materials it can be built from: an organic with conductive traces and vias, glass with the same, silicon with TSVs and dielectric layers, or ceramic. That menu lets the bridge interface to dies of different heights and pitches, which is exactly the mismatch a flipped, recessed HBM stack creates next to a tall compute stack.

Reading the claims as a set, the invention is less “flip the HBM” and more “rebuild the package around a flipped HBM”: invert the stack so the logic die faces the heat spreader, recess the memory into a substrate cavity to manage height, route through a bridge that sizes power and signal interconnects separately, and add secondary substrates so the whole thing meshes with neighboring dies. Each move exists to make the thermal flip survive contact with the electrical and mechanical realities of a real accelerator package.

For the reader, the anatomy point is that an HBM stack's usable performance is thermally limited, and packaging engineers are willing to flip the whole device - and sink it into a cavity - to manage it. Intel's application is a directional claim on doing exactly that: treating orientation as a cooling tool while sizing power and signal interconnects, and adding bridge and secondary substrates, to keep the bandwidth.