What does Intel's newly issued glass-core packaging grant actually build? It positions integrated-circuit dies both above and below a single glass layer and drops a silicon bridge die into a cavity cut clean through that glass, so the dies on either side talk to each other through the bridge. Grant US12672564B2 ("Technologies for vertically interconnected glass core architecture," issued June 30, 2026, assigned to Intel Corporation) is directed to exactly that structure, and the engineering payoff it names is three-dimensional heterogeneous integration with fine-pitch die-to-die connections. This is a granted patent, issued in the June 30 B2 drop, not a pending application.

Start with the problem the field is wrestling with. Advanced packages have become the real bottleneck of the AI buildout: raw transistor scaling matters less than how many dies you can stitch together at fine pitch on a flat, dimensionally stable substrate. Organic package substrates warp under thermal load and cannot hold the tightest via pitches; silicon interposers and 2.5D approaches deliver density but at cost and reticle-size limits. Glass sits in between — it is flat, thermally stable, and lets you drill through-glass vias (TGVs) at pitch. What this grant adds is verticality: instead of spreading dies across one face of an interposer, it uses the glass layer itself as a two-sided mounting plane with the interconnect bridge buried inside it.

Read the independent claim and the geometry does the work. A cavity is defined in the glass layer and extends the full thickness, from the plane of the top surface to the plane of the bottom surface. A bridge die sits in that cavity. One or more dies above the glass layer are bonded to the bridge die, and one or more dies below the glass layer are bonded to the same bridge die. Dependent claims fill in the fabrication vocabulary: through-glass vias filled with copper pillars carry signals past the bridge, and those TGVs are recited at a pitch of less than 25 micrometers (claims 2, 3). Claim 15 recites hybrid bonding between the contact pads of the upper dies and the pads of both the bridge die and the glass layer — direct copper-to-copper and dielectric-to-dielectric bonding rather than solder microbumps.

Technologies for a vertically interconnected glass layer architecture is disclosed. In the illustrative embodiment, an integrated circuit component includes several integrated circuit dies and a glass layer. Integrated circuit dies are positioned both above and below the glass layer. The glass layer has a bridge die embedded in a cavity. The bridge die provides interconnects between the various dies and to other components off of the integrated circuit component. The glass layer can enable three-dimensional heterogeneous integration, allowing for fine pitch connections between dies.— Technologies for vertically interconnected glass core architecture, US12672564B2

Where it sits in the state of the art

Embedded silicon bridges are not new in principle — the industry already routes fine-pitch die-to-die links through bridge chips laminated into organic substrates. What the disclosed approach changes is the medium and the axis. By making the carrier a glass layer and sinking the bridge into a full-thickness cavity, the grant describes bonding dies on both faces, which folds a 2.5D bridge into a 3D stack. The dependent claims sketch how far the disclosure reaches: claims 4 through 6 recite stacking a second and third glass layer, each with its own cavity, bonded either with a bond film or by direct glass fusion. Claims 8 and 9 recite photonic integrated-circuit dies above the glass with waveguides defined in both the glass and the photonic die, photonically coupled — an optical-I/O path built into the package. Claim 12 recites the upper dies as high-bandwidth-memory dies, and claim 14 recites the copper TGV pillars doubling as a thermal path from the lower dies to a heat sink.

The single grant is part of a tightly themed Intel cluster in the same June 30 issue, and the cluster reads as one packaging program rather than scattered filings. US12672562B2 ("Cavity-less interconnect component on glass core") describes the complementary case where the interconnect bridge sits on top of a planar glass layer, surrounded by mold, instead of inside a cavity. US12672239B2 ("Hybrid bonded passive integrated devices on glass core") hybrid-bonds discrete inductors and capacitors directly onto the glass, moving passives off the board and into the substrate. US12672559B2 ("Low insertion loss coaxial through-hole for high-speed input-output") builds a coaxial TGV — a signal via ringed by a grounded conductive layer — for high-speed I/O, and US12672566B2 ("Wireless chip-to-chip high-speed data transport") reaches in the other direction with microbump-antenna wireless die-to-die links.

Around that packaging core, the same issue carries Intel device-level grants that show where the dies being packaged are heading. US12672347B2 ("Lower device access in stacked transistor devices") is directed to a conductive feature that reaches a lower source/drain region toward the backside of a stacked-transistor structure — backside-power territory. US12672349B2 ("Device, method and system to provide an interconnect between channel structures") is directed to an interconnect that extends between the channel structures of two transistors. And US12672256B2 ("Immersion cooling system with phoretic force particulate collection") addresses the thermal side of dense packaging, describing a particle collector for the dielectric liquid a chip package is immersed within.

What the record shows

The engineering thread is consistent: glass as a package medium, a bridge die for fine-pitch die-to-die routing, copper-filled through-glass vias at sub-25-micrometer pitch, hybrid bonding in place of solder, and headroom for stacked glass layers, embedded photonics, HBM, and integrated thermal paths. Every specific above is drawn from the issued claims and abstract of US12672564B2 and the abstracts of the companion grants, all assigned to Intel Corporation and all issued in the June 30, 2026 grant drop. These are issued grants, not applications; what they cover is the structure the claims recite, and nothing here speaks to which products, if any, implement it, or to any roadmap node.