It is instructive to follow one invention from application to grant. Intel's sparse-matrix systolic-array work - publishing as an application in 2022 - issues as a granted patent in 2024, and the maturation is exactly what the chipdocket house rule cares about: an application is not a grant.
The grant US12039001B2 (issued July 16, 2024; Intel Corporation; CPC G06F 17/16 matrix computation, G06F 9/3001 arithmetic instructions, G06F 9/30145, G06F 15/8046 array processors) issues on scalable sparse-matrix multiply acceleration using systolic arrays with feedback inputs - the same invention, now with examined claims.
Why does the grant matter beyond the application? A published application discloses what you intend to claim; a grant means a patent office examined those claims and allowed them, making them enforceable. For competitive analysis, the grant - not the application - is what carries legal weight, and its claims may be narrower or differently scoped than the application suggested.
The underlying engineering is unchanged and still compelling: skip the zeros in sparse AI matrices, and feed partial results back so a fixed-size systolic array handles larger problems. But now the right to exclude others from that specific approach is, in principle, in force.
Seen across the timeline, Intel's AI-math IP went from disclosure (2022 application) to grant (2024), tracking the broader AI-hardware buildout. The patent system's lag means much of the foundational accelerator IP being granted now was filed before the current demand surge - announced is not shipping, and filed is earlier still.
For the reader, the discipline is the takeaway: when assessing who owns AI-accelerator math, distinguish pending applications from issued grants. Intel's 2024 grant is the latter - an examined, enforceable claim on a core sparse-matrix technique - and that distinction is the whole point of reading the record carefully.