Underneath every AI accelerator is the same operation: multiply big matrices together, billions of times. The hardware that does it efficiently is a systolic array - a regular grid of multiply-accumulate cells that passes operands rhythmically through the array. Intel's 2022 filings stake claims in this space.
The application US20220156343A1 (published May 19, 2022; Intel Corporation; CPC G06F 17/16 matrix computation, G06F 9/3001 arithmetic instructions, G06F 15/8046 array processors) describes scalable sparse-matrix multiply acceleration using systolic arrays with feedback inputs. The same invention later issued as grants in the family, but the published application stakes the early priority.
The 'sparse' qualifier is where the engineering lives. Real AI matrices are often mostly zeros, and multiplying by zero is wasted work. A sparse-matrix accelerator skips the zeros, so the array spends its cycles on the nonzero math that actually matters - a large efficiency win if you can route the irregular data correctly.
'Feedback inputs' is the structural twist that makes it scalable. Feeding partial results back into the array lets a fixed-size grid handle larger or more complex multiplications than its raw dimensions would suggest, which is how you build an accelerator that scales without an impractically huge array.
Reading the assignee facets across the AI-math space, Intel files heavily here alongside NVIDIA and specialists like SambaNova - a genuine thicket around how to do matrix multiply in silicon. This one application is a single, datable coordinate in that larger competitive map.
For the reader, the takeaway is that AI-accelerator IP is, at bottom, matrix-math IP. Intel's 2022 sparse-systolic filing - classified squarely in G06F 17/16 - is a claim on doing that math faster by not doing the useless parts, and it predates much of the current AI-hardware hype cycle.