As advanced packaging migrates from organic and silicon interposers toward glass cores, a stubborn materials problem moves to the foreground: glass and the copper that fills its vias do not expand at the same rate. Every thermal excursion, from reflow to field operation, loads the glass-metal interface, and glass is unforgiving of tensile stress. A newly published Intel application, US20260198346A1, is directed to that interface, and its answer is to stop treating the via liner as a single film.

The disclosure describes a through-glass via lined not once but twice. A first liner sits directly on the glass sidewall; a second liner is interposed between that first liner and the conductive material that fills the via. What makes the pair more than redundant is the modulus grading between them. The application specifies a first liner formed from an inorganic material with a first Young's modulus, and a second liner from an inorganic material whose Young's modulus is lower than the first. In the disclosed embodiments the first liner falls between 25 and 50 GPa while the second sits between 1 GPa and less than 25 GPa, so stiffness steps down as you move inward toward the metal.

The reasoning an informed reader can extract is straightforward. A stiffer film anchored to the rigid glass keeps the sidewall well defined and mechanically coupled to the core, while a compliant inner film gives the system somewhere to accommodate the strain that the expanding and contracting via metal imposes. Rather than presenting a single abrupt stiffness discontinuity at the glass-metal boundary, the double liner distributes the transition across two interfaces, which the filing frames as a route to alleviating via stress. Here is how the abstract states the mechanism:

Disclosed herein are microelectronic assemblies and related devices and methods for alleviating stresses in through-glass vias by providing double liner materials. In some embodiments, a microelectronic assembly may include a glass layer having a first surface and an opposing second surface; a via extending through the glass layer between the first and second surfaces, the via including a conductive material; a first liner, on a sidewall of the glass layer in the via, including a first inorganic material having a first Young's modulus; and a second liner, between the first liner and the conductive material of the via, including a second inorganic material having a second Young's modulus that is less than the first Young's modulus. In some embodiments, the first Young's modulus is between 25 Gigapascal (GPa) and 50 GPa, and the second Young's modulus is between 1 GPa and less than 25 GPa.— MICROELECTRONIC ASSEMBLIES INCLUDING DOUBLE LINERS IN THROUGH-GLASS VIAS, US20260198346A1

The materials and the geometry

The application also gives the films chemical identities. The first liner may include silicon and oxygen, consistent with a silicon-oxide-type film in the stiffer 25 to 50 GPa range. The second liner is described as including silicon, oxygen, and carbon, optionally with fluorine added, the kind of carbon-doped or fluorine-modified oxide chemistry associated with lower-modulus, more compliant dielectrics. In other words, the modulus grading is achieved by chemistry the industry already knows how to deposit, rather than by an exotic material.

Geometry matters as much as chemistry here. The filing contemplates vias with aspect ratios from 4:1 up to 30:1 through glass cores ranging from 50 micrometers to 2 millimeters thick. High-aspect-ratio vias are precisely where liner conformality and interface stress become difficult, because the sidewall area over which stress accumulates grows with depth. Independent claim 1 tracks the abstract closely, reciting the glass layer, the conductive via, the first liner on the sidewall with its first Young's modulus, and the second liner between at least a portion of the first liner and the conductor with a lower second modulus. A separate embodiment folds the same structure into an IC package: a glass core carrying conductive vias, each with the double-liner layer.

Where it sits beside the granted cohort

US20260198346A1 is a published application, still pending rather than granted, and it surfaces the same week as a cluster of Intel packaging patents that did issue. The glass-substrate theme recurs among them: US12677688B2 covers coaxial inductors fabricated through a drill-less via process on a glass substrate, using an hourglass-profile via opening filled with a magnetic layer. Package routing shows up in US12677682B2, which is directed to multi-layered metallization lines built as a plated copper bulk on a non-copper seed for die-to-die signaling, and US12677375B2, a stepped package with recessed circuit board and stepped conductive-contact portions.

Two further grants round out the same-week set on the integration side. US12677699B2 describes silicon carbide power devices integrated with silicon logic through wafer-scale layer transfer, and US12676606B2 is directed to a series-transistor over-voltage protection circuit. Read together, the pending double-liner filing and the granted packaging patents describe sustained engineering around glass cores and the thermomechanical realities of building on them, with the via liner being one of the finer-grained problems that the glass transition surfaces.

For readers tracking the field's state of the art, the double-liner approach is notable less for any single material choice than for how it reframes the liner. Treating it as a two-layer stiffness gradient rather than a single passivation film is a design move that maps cleanly onto existing oxide-deposition tooling while addressing the specific failure mode glass introduces. Whether the pending claims issue as filed remains to be seen, but the disclosed structure is a concrete engineering account of what it takes to keep metal-filled vias from cracking their glass host.