The hard problem in a large accelerator package is not making two dies talk to each other. It is making two dies talk to each other and getting everything else — power, lower-speed signalling, the routes that need to reach the far side of the package — past the structure that makes the first thing possible. A silicon bridge buys enormous wiring density over a short span, but it is a slab of silicon sitting in the middle of the vertical path. Anything that needs to go from the package substrate to the top tier has to go around it.

A patent application published on August 6, 2026 — US20260231831A1, assigned to Intel Corporation — is directed at that routing problem. The structure it describes has two redistribution layers. The lower one couples to the package substrate through interconnects surrounded by underfill. Above it sit three dies: a first, a second and a third, with the second laterally between the other two. The first and third dies contain through-silicon vias. The second does not. Above that layer, a second redistribution layer carries the compute tier.

The routing answer is the conductive pillars. They stand in the insulating material alongside the three dies, laterally spaced from all of them, and — the recited detail that matters — they have the same vertical thickness as the insulating material itself. That is what makes them a through-path: the pillar spans the full height of the bridge tier, so the second redistribution layer connects to the first one directly, without transiting a die. The application places a subset of pillars between the first and second dies and another subset between the second and third, which is to say between the bridges rather than only around the perimeter.

wherein the first surfaces of the second and third dies have a combined surface area between 3,000 square millimeters (mm2) and 9,000 mm2— HIGH PERFORMANCE MICROELECTRONIC ASSEMBLIES INCLUDING THROUGH-SILICON VIA BRIDGES WITH TOP DIE FIRST APPROACH, US20260231831A1

That sentence is from the abstract, and it is worth being precise about where it sits. The 3,000-to-9,000-square-millimetre range is a striking number — the upper end is several times the reticle limit, which is the regime that forces a package like this in the first place. But the range does not appear in any of the twenty claims. The independent claims recite the structure and the die roles; they do not recite an area. The abstract and the claim set describe the disclosure at different levels of generality, and the area figure belongs to the former.

Claims that name the payload

What the claims do recite is unusually specific about what the package is carrying. Claim 1 does not say “a fourth die” and “a fifth die.” It says a first high bandwidth memory over the first die, a first graphics processor unit die over the first and second dies, a second GPU die over the second and third dies, and a second HBM over the third die — each coupled to the second redistribution layer by its own set of interconnects, each laterally spaced from its neighbour. The floorplan is memory, compute, compute, memory, and the two GPU dies each straddle the middle bridge. The middle die, the one without TSVs, is positioned to be the die-to-die link between the two processors.

Two dependent claims add a geometric constraint that reads like an assembly consequence rather than an electrical one. Claim 5 puts the top surfaces of the two GPU dies at the same level; claim 6 then puts those surfaces at a different level from the tops of the HBM stacks. Co-planarity across the two compute dies matters for a heat spreader. The memory stacks, being a different height, are explicitly not required to join that plane. Claim 2 adds that each of the three lower dies is thinner than the insulating material around them — consistent with the pillars, not the dies, defining the tier height.

The application carries three independent claims. Claim 1 is the assembly with HBM named. Claim 8 is the same assembly with the memory recited generically as a first and second “memory die.” Claim 14 is a method of fabricating the claim 1 structure. Readers comparing claims 1 and 8 side by side should note that the material ordinals shift between them: what claim 1 calls an “underfill material” between the first RDL and the substrate, claim 8 calls a “first insulating material,” which pushes every subsequent insulating-material number up by one. The structures correspond; the labels do not.

Where it sits in the day's filings

The title's “top die first” phrase points at assembly order — building the upper tier before committing it to the lower one, which is the standard answer to yield loss when an expensive compute die is attached late. Intel published fifteen other applications the same day, and the packaging cluster around this one is substantial. A disaggregated-package application describes a bridge die with IC dies directly on it and no redistribution layer in that path at all — the inverse trade-off to the one above. Another runs common metallization layers across two chiplets bonded to a shared base. A third addresses head-and-pillow solder defects with a low-temperature solder cap that melts early and bridges the gap during thermal compression bonding — a failure mode that gets worse as die counts and warpage rise.

Two further applications work the protocol layer of the same problem. A die-to-die adapter selects a data format for a D2D link based on the link's parameters; a clock-phase application holds the clock roughly 90 degrees from the data phase at the receiving die. Neither is about packaging geometry, but both are about the same seam. Alongside them the day's set includes stacked memory with multilayer continuous vias and a parallel-flow immersion cooling apparatus, plus a separate AI-datapath group covering FP4 arithmetic via scaled 5-bit integers, on-chip decompression and sparsity decode, and reinforcement-learning across heterogeneous processors.

Read together, the day's disclosures describe a machine from the solder joint up to the number format. The bridge application is the part that decides where the wires go. It is a published application, not a granted patent, and its claims have not been examined to allowance; what is on the record is the architecture its drafters chose to describe, down to naming the accelerator parts by function.