The shortest wire is the fastest and the most efficient, so the logical extreme of memory integration is to put the memory directly under the compute. Kepler Computing's 2025 grant claims exactly that: an AI processor with DRAM stacked beneath the processor die.
The grant US12283571B1, "Ultra high-bandwidth artificial intelligence (AI) processor with DRAM under the processor" (issued April 22, 2025; Kepler Computing Inc.; CPC H01L 25/0657 stacked-die assembly, H01L 23/49894 substrate, H10B 41/42 memory device) claims the architecture. The H10B 41/42 memory classification alongside the stacked-die code confirms it is DRAM integrated vertically with the logic.
Do the bandwidth math on why 'under' beats 'beside.' An interposer-based design routes HBM bandwidth sideways across millimeters of silicon; putting DRAM directly under the processor collapses that to a vertical hop of microns. Shorter paths mean you can run wider and faster at lower energy per bit - the trifecta AI compute is starving for.
It also sidesteps the interposer chokepoint. If the memory is stacked vertically beneath the compute rather than spread beside it on a large interposer, you reduce dependence on the scarce interposer capacity that has gated the AI buildout - a strategic as well as a performance argument.
Kepler Computing is a startup pursuing aggressive AI-memory integration, and seeing a granted DRAM-under-processor claim from a startup signals that the most extreme integration ideas are being pushed by focused new entrants, not only the incumbents. The architecture space is still open enough to stake bold claims.
For the bandwidth reader, the through-line of this whole sector is visible here: every advance - wider stacks, tiering, compute-in-memory, on-stack regulation - is about getting memory closer to compute. Kepler's 2025 grant takes that to its limit, putting the DRAM directly underneath, and claims the result.