Reliability logic in memory faces an architectural choice: spread the error correction across many local circuits, or centralize it in one block that the whole device routes through. Micron's 2024 grant claims the centralized design.
The grant US11990199B2, "Centralized error correction circuit" (issued May 21, 2024; Micron Technology, Inc.; CPC G11C 29/42 ECC in memory, G11C 29/1201 testing, G11C 29/4401 redundancy/repair), claims a centralized error-correction circuit. The G11C 29/42 code is the memory-array error-correction classification.
Centralizing has clear trade-offs. The upside: one well-optimized correction block is cheaper in area and easier to upgrade than many scattered ones, and it gives a single point to manage the device's reliability policy. The cost: everything funnels through it, so it must be fast and wide enough not to become a bottleneck - which is where the design effort goes.
Contrast with Samsung's selective-parallel approach the same year and you see two memory vendors making different bets on the same problem. Samsung emphasizes spreading and parallelizing the work to hide latency; Micron emphasizes consolidating it for efficiency and manageability. The patent record captures a genuine design debate.
For bandwidth, the centralized circuit's throughput is the thing to watch. If it can keep up with the array's access rate, you get efficient reliability; if it cannot, it caps effective bandwidth. The value of the claim is in a centralized block engineered to serve the whole device without throttling it.
For the reader, the lesson is that 'memory reliability' hides real architectural choices with bandwidth consequences. Micron's 2024 centralized-ECC grant stakes out one side of that choice - and reading it next to Samsung's shows how the leading memory makers diverge on how to make dense memory both fast and trustworthy.