Every leading-edge logic node now talks about gate-all-around, but the device underneath the acronym is concrete and worth seeing plainly. A nanosheet transistor is a vertical stack of thin silicon sheets, each acting as a channel, with the gate material filling in completely around every sheet.
The 2020 grant US10727315B2 (issued July 28, 2020; Tessera, Inc.; CPC H01L 29/0673 for the stacked nanosheet channel, H01L 29/42392 for the wrap-around gate, H01L 29/775) claims the nanosheet transistor structure itself. The H01L 29/0673 code is the signature of a multi-sheet channel; H01L 29/42392 is the all-around gate.
Why wrap the gate all the way around? Control. In a planar transistor the gate touches the channel on one side; in a finFET, three sides; in a nanosheet, all four. More gate contact means the transistor turns fully off with less leakage and switches more cleanly - the reason the industry moved to this geometry as fins ran out of room to shrink.
The stacked-sheet arrangement also buys you effective width. Stacking three or four channels in the footprint of one gives you more current-carrying area without spreading sideways, which is how you keep drive strength up while the cell shrinks. The structure in this grant is what makes that trade work.
Assignment is part of the story. Tessera (a licensing entity) holding a foundational nanosheet grant from 2020 is a reminder that core device IP often sits with IP-holding companies and research IDMs rather than the foundry that eventually ships the node - the claim was filed long before any GAA product reached customers.
Read the claim, not the brand. "Gate-all-around" is a marketing term; the patent describes a specific physical object - sheets, gate, source/drain - and that object, filed and granted in 2020, is what every 2nm-class roadmap is now built around.