Every leading-edge logic node now talks about gate-all-around, but the device underneath the acronym is concrete and worth seeing plainly. A nanosheet transistor is a vertical stack of thin silicon sheets, each acting as a channel, with the gate material filling in completely around every sheet.

The 2020 grant US10727315B2 (issued July 28, 2020; Tessera, Inc.; CPC H01L 29/0673 for the stacked nanosheet channel, H01L 29/42392 for the wrap-around gate, H01L 29/775) claims the nanosheet transistor structure itself. The H01L 29/0673 code is the signature of a multi-sheet channel; H01L 29/42392 is the all-around gate.

“Inner and outer spacers for nanosheet transistors are formed using techniques that improve junction uniformity. One nanosheet transistor device includes outer spacers and an interlevel dielectric layer liner made from the same material.”— U.S. Patent No. 10,727,315 source

Why wrap the gate all the way around? Control. In a planar transistor the gate touches the channel on one side; in a finFET, three sides; in a nanosheet, all four. More gate contact means the transistor turns fully off with less leakage and switches more cleanly - the reason the industry moved to this geometry as fins ran out of room to shrink.

What the claim actually protects, though, is narrower and more interesting than “a nanosheet transistor.” The novelty the abstract advertises is in the spacers - the small dielectric structures that wall off the gate from the source/drain regions - and the technique for forming them “to improve junction uniformity.” Junction uniformity matters because in a stack of three or four channels, each sheet's source/drain junction has to come out the same; ragged, uneven junctions are exactly what kills yield and performance as you multiply channels vertically. The patent's contribution is making the inner spacers (between the sheets) and outer spacers (along the gate sidewalls) controllable enough to keep those junctions consistent.

Claim 1 lays out the full device: a vertical stack of nanosheet channel layers, all-around gate stacks pairing a gate dielectric with metal gate material wrapped around each sheet, a gate electrode rising vertically with two sidewalls, and epitaxial source/drain regions on either side. The distinctive feature is a single “dielectric liner” that does double duty - it both caps the source/drain regions and forms the outer spacers along the gate sidewalls, with those two functions made “integral” from one continuous material. Building the liner and the outer spacer as one piece is the manufacturing trick: fewer separate depositions, better-controlled geometry, more uniform junctions.

The dependent claims sharpen the materials and dimensions. Claim 2 sets the channel sheets between ten and one hundred nanometers wide - the literal nanosheet width that names the device. Claim 3 specifies the dielectric liner consists essentially of SiCO (a silicon-carbon-oxygen dielectric), and claims 4 and 6-7 extend the same-material idea inward: a dielectric inner spacer sitting between each channel layer, positioned between the all-around gate stacks and the source/drain regions, made of the same SiCO as the liner (claim 6) - or, in a variant, an inner spacer of silicon dioxide paired with a SiCO liner (claim 7). Claim 9 confirms the channels are essentially monocrystalline silicon. These are not decorative details; the whole point of the grant is that picking one dielectric for liner, outer spacer, and inner spacer simplifies the process flow while holding junction uniformity across the stack.

The stacked-sheet arrangement also buys you effective width. Stacking three or four channels in the footprint of one gives you more current-carrying area without spreading sideways, which is how you keep drive strength up while the cell shrinks. The structure in this grant - and specifically its disciplined spacer scheme - is what makes that trade work in production rather than just on paper.

Assignment is part of the story. Tessera (a licensing entity) holding a foundational nanosheet grant from 2020 is a reminder that core device IP often sits with IP-holding companies and research IDMs rather than the foundry that eventually ships the node - the claim was filed long before any GAA product reached customers.

The structural detail in claim 1 repays a close read because it explains why the spacer scheme is hard. The gate dielectric is described as having vertically extending portions formed on the outer spacer portions of the liner, sitting between the gate electrode's sidewalls and those outer spacers - meaning the same dielectric liner that caps the source/drains also defines the boundary the gate dielectric grows against. The interlevel dielectric layer then extends over the liner portions covering the source/drain regions. Building one continuous liner that has to play all these roles - source/drain cap, outer spacer, and reference surface for the gate dielectric - while staying integral and uniform is precisely the process control the patent is claiming. Claim 5 anchors the whole stack on a semiconductor substrate with an oxide layer, the channel sheets extending vertically from it and the liner including horizontal portions resting on that oxide.

The materials choices in the dependent claims are not arbitrary either. SiCO is a low-leakage, etch-selective dielectric; using it for the liner (claim 3), and optionally for the inner spacers too (claim 6), lets the inner and outer spacers be formed and protected together, which is what keeps the buried source/drain junctions between the sheets uniform. The silicon-dioxide-inner-spacer variant in claim 7 is the alternative the inventors carved out as a fallback. Each of these is a small lever on the same goal the abstract states up front: forming the spacers “using techniques that improve junction uniformity” across a multi-sheet stack.

Read the claim, not the brand. "Gate-all-around" is a marketing term; the patent describes a specific physical object - silicon sheets ten-to-one-hundred nanometers wide, a wrap-around metal gate, integral SiCO inner and outer spacers, and epitaxial source/drains - and that object, filed and granted in 2020, is what every 2nm-class roadmap is now built around.