Gate-all-around (GAA) transistors — in which stacked horizontal silicon sheets are fully wrapped by the gate, rather than straddled on three sides as in a FinFET — are the architecture every leading-edge foundry is moving to at the 2nm-class node. A group of applications published in this week's drop and assigned to Samsung Electronics (Samsung), classified under CPC H10D 84/856 and neighboring transistor subclasses, is directed not at the channel itself but at a quieter scaling problem: how to keep adjacent GAA devices electrically separate, and how to isolate the source/drain regions stacked above them, once there is almost no horizontal room left to do it.

The hero application, "Multiple Gate-All-Around Semiconductor Devices With Gate Separation" (US20260173520A1), describes a substrate carrying a first and second channel structure side by side, each with its own gate structure, and a gate-separation pattern placed between the two gates. The disclosed separation pattern sits at a level lower than the top surface of either gate, with a gate capping layer above. In plain terms, the application is directed to a recessed insulating divider between neighboring transistors — a structure that matters because, as device pitch shrinks, the dielectric wall that keeps one gate from shorting to the next has to occupy a vanishingly small slot without compromising the gate metal on either side.

A semiconductor memory device includes: a substrate having a first channel structure and a second channel structure respectively extending in a first direction and arranged in a second direction perpendicular to the first direction; a first gate structure disposed on the first channel structure and extending in the second direction on the substrate; a second gate structure disposed on the second channel structure and extending in the second direction; ... a gate separation pattern disposed between the first and second gate structures and having an upper surface at a level lower than that of an upper surface of each of the first and second gate structures, including a first insulating material; and a gate capping layer disposed on the first and second gate structures.— MULTIPLE GATE-ALL-AROUND SEMICONDUCTOR DEVICES WITH GATE SEPARATION, US20260173520A1

Why gate separation is the scaling pinch point

In a FinFET, separating two devices was largely a matter of the fin-cut and the dielectric between fins. In a nanosheet GAA device the gate metal wraps the channel on all four sides, which means the metal fills the gaps between stacked sheets and extends laterally toward its neighbor. The "diffusion break" or gate-cut that used to be comparatively forgiving now has to land a precise insulating pattern between two gates whose metal is only nanometers apart. The hero application's recessed separation pattern — below the gate tops, capped from above — is one disclosed answer: it lets the cut be defined without having to perfectly co-planarize the divider with the gate metal, which is exactly the kind of process margin that gets scarce at tight cell heights.

A companion application, US20260173518A1, attacks the same isolation theme one level deeper. It discloses a first channel structure split into a first and second sheet by an insulating pillar running vertically through the channel, with a second insulating pillar separating a third and fourth sheet nearby. Putting a dielectric pillar inside what would otherwise be a continuous sheet is a way to define two independent channels in the footprint that previously held one — a structure relevant to forked-sheet and stacked-FET layouts where the goal is to pack more drive into a fixed track width.

The source/drain regions stacked above the channel

Isolation does not stop at the gate. US20260173511A1 is directed to a device with a first active pattern of stacked sheets and a second active pattern above it, each with its own source/drain region, where a fence layer surrounds the lower source/drain pattern and the upper source/drain pattern is wider than the lower one. That vertically stacked source/drain arrangement is the signature of a complementary-FET (CFET) style layout — nFET over pFET in the same column — and the fence layer is the disclosed mechanism for keeping the lower epitaxial region from merging into its neighbor as the two tiers are built. The differing widths between the fenced lower region and the unfenced upper region are the kind of asymmetry that falls out of building two device tiers in sequence.

US20260173507A1 adds a layout-level variable to the same family: a multi-region device in which a first region has fewer stacked gate-channel layers than a second region, with the lowermost gate in the first region sitting higher than the lowermost gate in the second. The application is directed to mixing devices with different sheet counts — and therefore different drive strength — on a single die, which is how a designer trades performance against area cell by cell. Read alongside the gate-separation and stacked-source/drain disclosures, it sketches a toolkit for tuning a nanosheet platform rather than a single fixed device.

Two more applications in the drop fill in the fabrication and wiring side. US20260173495A1 discloses a method of forming separate work-function metal layers over first and second active regions using an organic sacrificial pattern and a heat-treatment crosslinking step — the work-function metal being what sets a GAA transistor's threshold voltage, and the n/p patterning of it being one of the harder steps once the metal has to fill the narrow gaps between wrapped sheets. US20260173847A1, meanwhile, is directed to a horizontally-extending middle-of-line (MOL) structure with an active via connecting an active contact to at least two wiring patterns — a contact-layer detail that becomes load-bearing when the transistors below have been packed this tightly and every local interconnect has to be placed with no slack.

None of these applications is a granted patent; each is a published application disclosing an approach, and the independent claims define the scope being sought. Taken together, the cluster is directed less at the headline "nanosheet channel" than at the surrounding structures — the gate cut, the in-channel pillar, the stacked source/drain fence, the work-function metal patterning, the MOL via — that determine whether a GAA platform actually yields at tight pitch. That focus is itself the signal: in this week's drop, the disclosed engineering effort sits in the isolation and integration layer around the transistor, which is where leading-edge logic scaling tends to get gated. For the IP-landscape view of these filings, chipclaims tracks the GAA claim language; for the capacity and capex context, hardwareledger reads the foundry filings.