Reliability and speed pull against each other in dense memory. The denser the cells, the more bit errors creep in, so error-correcting code (ECC) becomes mandatory - but checking and correcting every access can add latency. Samsung's 2024 grant tries to get the reliability without paying full freight on speed.
The grant US12079080B2 (issued September 3, 2024; SAMSUNG ELECTRONICS CO., LTD.; CPC G06F 11/1068 memory error correction, G06F 3/0619 / G06F 3/0659 storage access control) claims a memory controller that performs selective and parallel error correction. The G06F 11/1068 code is squarely the memory-ECC classification.
The two qualifiers are the invention. 'Selective' means not every access pays the full correction cost - the controller applies heavier correction where it is needed and a lighter path where it is not. 'Parallel' means the correction work overlaps with other operations rather than stalling them in series. Together they aim to hide the ECC latency.
Why this matters for bandwidth: a memory subsystem's effective throughput depends on latency as well as raw transfer rate. If every read waits on serial error correction, the achievable bandwidth drops below the headline number. Selective, parallel ECC is a way to keep effective bandwidth close to peak while still guaranteeing data integrity.
Samsung's dual role as memory maker and system designer shows again. This is controller IP - the logic that sits between the host and the memory array - and owning the controller is how a memory vendor differentiates on reliability and performance, not just capacity.
For the reader, the takeaway is that reliability has a performance cost, and the engineering frontier is hiding that cost. Samsung's 2024 grant claims a way to correct errors without serializing the memory pipeline - reliability that does not silently eat your bandwidth.