Building a memory stack is a two-part problem. Part one is physical: bond the dies, run the through-silicon vias. Part two is logical: make the stack behave like one addressable memory rather than a pile of separate chips. Samsung's 2023 grant covers both - the device and its operating method.
The grant US11599458B2 (issued March 7, 2023; Samsung Electronics Co., Ltd.; CPC G06F 12/06 memory addressing/allocation, G11C 8/00 memory addressing, H01L 23/481 through-substrate vias, H01L 25/0657 stacked-die assembly) claims a stacked memory device and how to operate it. The G06F 12/06 addressing code alongside the H01L stacking codes is the signature of a structure-plus-method claim.
Why does operation deserve its own claim? Because a vertical stack changes the access patterns. Reads and writes may target different dies in the stack, latency can vary by layer, and the controller has to schedule across the stack coherently. An operating method that handles this is what turns the physical stack into usable bandwidth.
Samsung's position as a top DRAM maker and HBM supplier makes this directly relevant to the AI buildout. Every accelerator that consumes HBM relies on stacked memory operating correctly under heavy concurrent access - the kind of behavior an operating-method patent like this addresses.
It is worth distinguishing this from the raw stacked-DRAM structure patents (like Rambus's earlier work). This grant's value-add is the operation: not just that the dies are stacked, but how the system reads, writes, and addresses across them. The method is the differentiator.
For the bandwidth reader, the lesson is that a memory stack's real-world throughput depends as much on the control logic as on the wire count. Samsung's 2023 grant claims that control layer, which is where a stack's theoretical bandwidth either becomes real or gets squandered.