There are three places you can move AI data, and the third is the least understood. Inside a die, it is on-chip wires. Between dies in a package, it is the die-to-die link. Across a rack — chip to chip, box to box — it is the scale-up interconnect, the fabric that stitches dozens or hundreds of accelerators into one system that behaves, as much as possible, like a single giant computer.
The names you hear are NVLink (NVIDIA's proprietary fabric), UALink (an open-consortium answer to it), and CXL (a memory-coherent standard riding on PCIe physical layers). What is easy to miss is how much they share underneath. UnifabriX's grant US12632404B2, "CXL over ScaleUp Ethernet (SUE), UALink, NVLink, ethernet, or PHY based on IEEE 802.3" (issued May 19, 2026; UnifabriX Ltd.), literally enumerates all of them — and frames them as protocol choices layered over a common high-speed physical layer (CPC G06F13/4221, around bus bridging).
That framing is the real story. The marketing war is over which logo wins — NVLink versus UALink versus CXL. The patent's view is more deflationary and more accurate: these are largely different transaction and coherence protocols sitting on top of the same class of fast serial PHY, including Ethernet-based physical layers from IEEE 802.3. If the wire is increasingly common, the competition shifts to the protocol stack, the coherence model, and the ecosystem — not the raw signaling.
Why does scale-up matter so much right now? Because a single AI training job no longer fits on one accelerator, or one box. The model and its activations are spread across many chips, and those chips must exchange gradients and parameters constantly. The scale-up fabric's bandwidth and latency set a hard ceiling on how efficiently you can run a job across many devices. Slow fabric means expensive accelerators sitting idle waiting on each other.
The competitive subtext is consolidation versus openness. NVLink keeps the fabric proprietary and the system vertically integrated; UALink and the CXL ecosystem try to commoditize it so multiple vendors' accelerators can share one fabric. A patent that treats all of them as PHY-plus-protocol variants is, in effect, betting that the physical layer converges and the value moves up the stack — which is exactly where an independent fabric vendor would want the fight to be.
So the next time the conversation is "NVLink versus UALink," remember what the 2026 record shows: under the logos is a shared idea of fast serial links carrying different coherence protocols. The interconnect that ties the AI datacenter together is becoming a protocol contest fought on increasingly common wires — and the IP is being staked across all of them at once.