The marketing story of HBM is an AI story: GPUs starved for bandwidth, memory sold out for years. But the engineering idea - stack DRAM dies on top of each other and wire them through the silicon - is older than the demand, and the patent record proves it.
Rambus's grant US10614859B2 (issued April 7, 2020; Rambus Inc.; CPC G11C 5/063 stacked memory packaging, H01L 23/481 through-substrate vias, H01L 25/0657 stacked-die assemblies) claims a stacked DRAM device together with its method of manufacture. The presence of the H01L 23/481 TSV classification is the tell: this is vertical integration, not a flat module.
Do the bandwidth math on why anyone stacks at all. A flat DRAM talks to its host across a relatively narrow bus limited by package pins. Stack the dies and run thousands of TSVs straight down, and the effective interface width explodes - which is precisely how HBM reaches its headline GB/s figures. The structure in this grant is the physical precondition for that width.
Rambus is a licensing-first company, which makes the timing meaningful. Filing a manufacturing method for stacked DRAM in the late 2010s is a bet that everyone would eventually need to build memory this way - a bet that paid off when HBM became the gating resource of the AI buildout.
It is worth separating the concept from the modern HBM spec. This grant is not HBM4; it is the underlying notion that a DRAM device can be a vertical stack with a defined manufacturing flow. The JEDEC stack heights, the channel counts, the thermal handling - those are later refinements layered on top of this base idea.
The takeaway for the bandwidth-watcher: when you read about an HBM shortage, remember the supply chain is built on a decade of stacked-memory IP. The 2020 record shows the foundation was poured long before the building boom.