Follow the tool, not the chip. Wafer-to-wafer bonding is the enabling step behind stacked memory, backside power and every flavour of 3D integration, and its hard limit is not adhesion — it is alignment. Two wafers that each look acceptable on their own will not agree with each other once pressed together, because neither is flat. Each carries residual stress from hundreds of prior process steps, and that stress expresses itself as curvature, slope and in-plane distortion. Bond them and the features on one land somewhere slightly other than where the features on the other are waiting. That misregistration is overlay error, and at hybrid-bonding pitches it is the yield.

An application published on 30 July 2026 and assigned to Tokyo Electron Limited is about closing a loop around that problem. US20260223625A1, naming Nathan Ip as sole inventor, is classified under CPC H10P 72/0428 and H10P 72/0616 alongside G05B 19/4099 — a process-control code, which is the giveaway.

Measure first, then decide the recipe

The core idea in claim 2 is ordering. A metrology tool integrated with the bonding tool measures a physical parameter of the first wafer representing information relating to its topographical features. A tool controller holding a model of the wafer bonding process then generates the bonding recipe from that measurement. Only then does the bonding happen. The wafer's own shape is an input to how it will be bonded, rather than something discovered afterwards from a scrapped lot.

The claims are unusually specific about both halves. The physical parameter is at least one of overlay, in-plane distortion, slope, curvature, force or stress. The instrument is at least one of a dual Fizeau wafer interferometer, a Shack-Hartmann sensor, a PhotoStress analysis system, a wavefront phase sensor, a multi-beam reflectometry system, or capacitance sensors — and claims 16 and 17 pair particular instruments to particular quantities.

The method of claim 2, wherein: the physical parameter includes in-plane distortion (IPD), and the metrology tool comprises a dual Fizeau wafer interferometer configured to measure the IPD.— Integrated Metrology for Process Controls in Wafer Bonding System, US20260223625A1

Those pairings are engineering, not boilerplate. A dual Fizeau interferometer measures both wafer surfaces interferometrically and is the natural instrument for in-plane distortion. A Shack-Hartmann sensor reports local wavefront slope across an aperture, which claim 17 accordingly ties to the slope parameter. Naming a proprietary designation — PhotoStress — inside a claim is a narrower drafting choice, and the record supplies no further specification of it.

Where does the model come from? Claim 3 answers that with simulation rather than history: measure a third and a fourth wafer, simulate their bonding under given process conditions to estimate the post-bond result, and create the model from those measurements, those conditions and that estimate. Claim 5 then describes the model in use — estimate post-bond distortions of the wafer about to be bonded, tune the process conditions to optimise those estimated distortions, and generate the recipe from the tuned conditions. The tool is running a prediction of the bond before committing to it.

Three loops, not one

The application actually claims three distinct control topologies. Claim 2 is feedforward: measure the incoming wafer, set the recipe. Claim 10 is feedback: bond first, measure the resulting post-bond wafer, and generate a second recipe from that measurement for the next pair. Claim 8 stitches the two together inside the feedforward chain.

Claim 18 is the one that leaves the tool. It recites a first bonding system measuring a wafer, generating a recipe, bonding, and then transmitting either the measured parameter or the recipe to a second bonding system — which bonds its own wafers accordingly. Claim 21 closes that loop too, updating the recipe used by either system based on a later measurement. That is fleet-level process control: what one bonder learns about a lot propagates to the others rather than being relearned.

A detail worth noticing is that claim 10's instrument list is not identical to claim 2's. Claim 10 adds a scanning interferometric sensor, which claim 15 ties to measuring topography of the post-bond wafer. The feedback path gets an instrument the feedforward path does not, which makes physical sense — the thing being measured after bonding is a bonded stack, not a free wafer.

Two cautions on reading the record. This is a published application, not a granted patent; it is unenforceable in this form and its claims may narrow. And the published claim set carries clear traces of amendment: claim 1 is (canceled), so the set begins at claim 2, and the wafer ordinals do not run continuously — claim 2 bonds a first and second wafer and then jumps to a fifth and sixth producing a third post-bond wafer, with no third, fourth or second post-bond wafer introduced anywhere in that claim. Claim 10 does the same thing with a seventh and eighth. Claim 4 compounds it by depending from claim 2 while reciting terms that only exist in claim 3.

Tokyo Electron also had a bonding grant issue two days earlier, on 28 July: US12696826B2, covering a laser liftoff layer used to move a die between carrier wafers before bonding it to a wafer holding a second die. One record is about performing the bond, the other about deciding how. Filed and granted in the same week, they describe the same preoccupation from opposite ends. What makes the control layer the interesting half is that bonding is effectively irreversible. Etch a wafer wrong and there are rework paths; bond two wafers face to face at hybrid pitch and the value of both is committed at once. Any decision that has to be right before the press closes is a decision worth measuring for, and that is the economic logic the claim ordering encodes — metrology first, model second, recipe third, contact last.