Stacking dies vertically solves bandwidth and density, but creates a power-delivery headache: each layer needs clean, stable voltage, and pushing regulated power up through a tall stack invites droop and noise. TSMC's 2024 grant puts the regulator inside the stack, close to where the power is used.
The grant US12046580B2 (issued July 23, 2024; TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.; CPC H01L 25/0657 stacked-die assembly, H01L 24/08 and H01L 24/80 bonding) claims a low-dropout (LDO) regulator for 3D IC power delivery. The stacked-die and bonding CPC codes anchor it firmly in 3D integration, not board-level power.
Why an LDO specifically, and why inside? An LDO gives a clean output from a small voltage drop with fast response - ideal for delivering a stable rail right where a die layer consumes it. Integrating it into the stack means the regulated voltage travels the shortest possible distance to the load, minimizing the droop that distance and current would otherwise cause.
This reframes power delivery as a packaging problem, not just a board problem. The same instinct behind backside power - get the power network closer to and better matched to the load - shows up here as on-stack regulation. The stack does not just move data efficiently; it must condition its own power.
Coming from TSMC, the world's indispensable foundry and a 3D-packaging leader, this is the kind of IP that ends up under everyone's stacked silicon. Customers building 3D parts on TSMC's platform inherit the power-delivery problem, and the foundry owning a regulated-power solution is strategically tidy.
For the reader, the anatomy lesson is that a modern 3D part contains its own power-management silicon. TSMC's 2024 LDO grant claims regulating voltage inside the stack - a reminder that as integration goes vertical, functions like power regulation migrate into the package alongside the compute and memory.