For two years the gating constraint on AI silicon has shifted from raw wafers to how those wafers are stitched together. Advanced packaging - assembling logic and high-bandwidth memory into a single high-throughput module - is the chokepoint, and TSMC (TSM) keeps funding it in plain sight in its board filings.

In a board-action report on Form 6-K filed February 10, 2026, TSMC lists capital appropriations including the installation and upgrade of advanced technology capacity and the installation and upgrade of advanced packaging, mature and/or specialty capacity. The filing was surfaced through SEC filings, the SEC filing data API and evidence index, and the appropriation language is quoted from the document.

“Installation and upgrade of advanced technology capacity; 2) Installation and upgrade of advanced packaging, mature and/or specialty technology capacity; 3) Fab construction, and installation of fab facility systems.”— SEC filing (6-K) source

This is not a one-off. Across multiple 2025 board-action 6-Ks, TSMC repeats the same structure - advanced technology capacity, advanced packaging capacity, fab construction - as recurring line items in successive capital approvals. When a foundry routes capital to packaging quarter after quarter, that is a confession of where the demand actually sits.

What are the technologies? TSMC's annual report on Form 20-F for the year ended December 31, 2025 names its stacking and packaging solutions explicitly, including TSMC-SoIC and CoWoS advanced packaging services. CoWoS (chip-on-wafer-on-substrate) places multiple dies on a silicon interposer; SoIC stacks them vertically. Both are the assembly steps that turn discrete chips into an AI accelerator.

The reading discipline here is to treat board-action 6-Ks as a capex tell. A press release can call packaging strategic; a signed board appropriation funding it is the harder evidence. Read the appropriation line items in the 6-K directly to see where the foundry is actually pointing its capital.