Moving a chip's power rails to the underside of the wafer frees front-side wiring for signals, but it creates a physics problem that has nothing to do with lithography: a low-resistance backside contact needs silicon that is both heavily doped and electrically activated, and activation classically needs heat that the already-finished front side cannot survive. An application published Thursday by Taiwan Semiconductor Manufacturing Company, Ltd. — US20260206554A1, "BACK-SIDE IMPLANTATION AND NANOSECOND LASER ANNEALING FOR SOURCE/DRAIN REGIONS" — describes putting that heat only where it is needed, within about 10 nm of the backside surface, and nowhere else.

The record is a published application carrying an A1 kind code, not a granted patent: it has been laid open, not examined to allowance, and nothing in it establishes that the technique has been built. It lists 20 claims with two independent claims, 1 and 11, and names Yi-Rui Chen, Yu-Chang Lin and Ji-Yin Tsai as inventors. Its CPC (Cooperative Patent Classification) codes sit across H10D and H10P — transistor structures and their manufacture. The publication date is 2026-07-16; the filing and priority dates are not established by the record as read here. The constraint it addresses is thermal budget. Contact resistance falls as dopant concentration at the contact interface rises, but dopants only carry current once they are activated — sitting on lattice sites rather than scattered through damaged crystal — and getting them there means driving the silicon hot. By the time a process reaches the backside, the front side is finished: metal gates, work-function metals, the first silicide, early interconnect. Those structures are heat-sensitive. A furnace anneal, or even a millisecond spike, soaks the whole stack. The dopants want temperature; the finished front side cannot tolerate it.

What the disclosed sequence does

Claim 1 recites the order explicitly, and the order is the invention's premise. A first metal silicide layer is formed on the front side of an epitaxial source/drain region. After that silicide exists, a dopant is implanted into the same source/drain region from its back side. A nanosecond laser annealing (NSA) process is then run on that region from the back side, a second metal silicide is formed on the back side, and a backside contact is formed over it. The technique is written for a wafer whose front face is already committed — which is precisely the situation backside power delivery creates.

The implant does double duty: it delivers concentration — dependent claim 3 recites an atomic concentration greater than about 1×10²¹ atoms per cubic centimeter within the back side of the source/drain region — and, as a side effect, smashes the implanted zone into an amorphous, non-crystalline layer. The anneal that follows is confined along two independent axes. In depth, by wavelength: dependent claim 2 recites a laser wavelength less than about 400 nm, and short-wavelength light is absorbed essentially at the surface it strikes. In time, by pulse length: a nanosecond pulse deposits and dissipates its energy before heat diffuses far. Dependent claim 4 puts the energy density in a range from about 0.5 to 1.3 J/cm², and dependent claim 5 recites a surface heating temperature greater than about 700°C at the epitaxial source/drain region. Those numbers narrow claim 1; claim 1 itself requires none of them.

To activate dopants without affecting front-side components, a nanosecond laser annealing (NSA) process is applied. The NSA process uses lasers with wavelengths shorter than 400 nm. This causes localized heating within about 10 nm of the surface, activating dopants and recrystallizing part of the amorphous region into crystalline region, while thinning the remaining amorphous region.— BACK-SIDE IMPLANTATION AND NANOSECOND LASER ANNEALING FOR SOURCE/DRAIN REGIONS, US20260206554A1

The abstract's opening sentence is ungrammatical as published, and the passage above is quoted as the record prints it. What it describes is one pulse doing three jobs at once: activating the dopants, recrystallizing part of the amorphous zone back into crystal, and thinning what remains of it — dependent claim 12 quantifies that thinning as to less than half the amorphous region's initial thickness. The leftover thin amorphous layer is not waste. It is feedstock: a metal silicidation process consumes it and converts it into the backside silicide layer that the backside contact lands on. Claim 11, the second independent claim, walks the same sequence around a gate structure wrapping a semiconductive nanostructure, and it too carries source-record artifacts — it refers to "the thinned amorphous region" without a preceding thinning step to give the phrase an antecedent. The claims split the dopant chemistry by device polarity. A p-type source/drain with a germanium atomic concentration in a range from about 60 to 80% takes gallium (claims 6 and 7); an n-type source/drain with 6 to 10% phosphorus takes arsenic (claims 8 and 9). Claim 10 names a nanosheet field-effect transistor as a target device, but as one option among others — claim 1 says only "a transistor." Nanosecond laser annealing is not new to the industry and the filing does not claim it is; what is claimed is a specific application and ordering of it, run from the back side, after the front-side silicide, and feeding a silicidation step.

The rest of Thursday's TSMC drop

The company placed 33 publications in this drop. Six of them, independently of the hero, are about getting current into a transistor from underneath the wafer. US20260206281A1 describes a back contact reaching into a source/drain through its back surface, deeper than the proximal channel feature. US20260206291A1 gives two transistors backside contact plugs of deliberately different depths. US20260206290A1 does the same across logic and memory vias. US20260206244A1 uses a buried etch stop and sacrificial epitaxial layers so a via can land on the source/drain after substrate removal, and US20260206245A1 contacts one source/drain from both ends. US20260206217A1 splits a memory cell across both wafer faces entirely. These records share a publication date and an assignee; nothing in any of them links them to each other or to a common program.

Read a different way, the hero also sits alongside two records about heat placement rather than power. US20260206576A1 builds interconnect dielectrics from porous organic framework material claiming a dielectric constant of 2 or less together with a thermal conductivity of 1 W/(m·K) or more — conducting heat out of the interconnect while keeping capacitance down. US20260206498A1 puts a buffer layer with deliberately lower thermal conductivity between a storage element and its bottom electrode, trapping switching heat inside a memory cell. Confining heat to 10 nm, moving it out of a dielectric stack, penning it into a cell: three different answers to where the energy is allowed to go.

What the hero does not say is worth stating plainly. It names no process node, no product, and no competitor. It reports no yield, no wafer cost, and no measured performance delta — the abstract says the approach "can enhance electrical performance by improving dopant activation and reducing contact resistance," a capability, not a result, and the modal is the record's own. The "about 10 nm" figure is a heating depth from the backside surface, not a feature size. On the evidence in the document, TSMC has described a way to spend a large thermal budget in a very small volume, and has asked the USPTO to consider it.