Two-and-a-half-D packaging puts dies side by side on an interposer; true 3D stacking puts them on top of each other. The hard part of going vertical is orientation and connection: which surface bonds to which, and how power and signals cross the boundary. TSMC's 2021 application addresses exactly that.
The application US20210043547A1 (published February 11, 2021; TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.; CPC H01L 23/481 through-substrate vias, H01L 25/50 assembly of stacked devices, H01L 21/76898 TSV formation) describes front-to-back bonding with TSVs. As a published application, it signals direction - it is not yet a granted claim - which is the right way to read it.
Front-to-back is a deliberate choice. Bonding front-to-front puts two active surfaces nose to nose, which is great for short connections but constrains layout; front-to-back lets you stack dies like floors of a building, with TSVs as the elevator shafts carrying power down and signal up through the substrate of the upper die.
The dense thicket of H01L 2224 bonding sub-classifications in this filing is itself the story. TSMC is not claiming one trick; it is papering the bonding and via-formation space around 3D stacking, which is how a foundry builds a defensible packaging franchise (the kind it markets as SoIC).
Distinguish application from grant. This is a 2021 publication - a window into what TSMC was developing - and the prudent reading is that it marks intent and priority date, not a fenced, enforceable claim. The chipclaims-style discipline is to never treat a published application as a granted patent.
For the packaging reader, the durable lesson is that 3D stacking is a bonding-and-via problem before it is a transistor problem. TSMC's 2021 application stakes out the front-to-back approach early, which is consistent with a foundry that means to gate the AI buildout on packaging it controls.