When IBM and Tessera were filing device-level GAA IP, TSMC was doing its own foundry-level work, and the 2021 record shows it. The difference matters: a device patent claims the transistor; a foundry structure patent claims how that device fits into a manufacturable cell layout.
The grant US10923474B2 (issued February 16, 2021; Taiwan Semiconductor Manufacturing Co., Ltd.; CPC H01L 27/0922 CMOS structure, H01L 27/0207 cell layout, H01L 29/78696 GAA transistor) claims a semiconductor structure built around gate-all-around devices. The inventor, Jhon Jhy Liaw, is one of TSMC's most prolific standard-cell architects - his name on a patent usually signals layout-level IP.
The H01L 27/0207 classification - integrated-circuit cell geometry - is the tell that this is about how GAA devices are arranged on the die, not just the physics of a single transistor. Foundries win or lose on density, and density lives in the cell structure.
Timing again undercuts the roadmap narrative. This is a 2021 grant; TSMC's N2 (its first GAA node) entered volume only in the mid-2020s. The structural IP was locked down years ahead, which is exactly what you would expect from a foundry that intends to be first and wants the patent moat in place before the product.
It is also a useful corrective to foundry-marketing nodes. "2nm" is a marketing label, not a measured dimension; what actually changes is the device architecture - the move to GAA - and the cell structures that exploit it. This grant is a piece of that real change, dated and attributable.
Follow the inventor and the CPC, not the node name. A Jhon Jhy Liaw GAA cell-structure grant from 2021 tells you more about TSMC's leading-edge intentions than any roadmap slide - because it is the filed, examined, granted record of what they were actually building.