Backside power delivery (BSPDN, sometimes written as a backside power delivery network) is a way of building a transistor so that the wires carrying electrical power reach the device from the underside of the silicon wafer rather than from the top. In a conventional chip, both the signal interconnect — the wiring that moves data between transistors — and the power-delivery rails sit in the same stack of metal layers on the front side of the wafer, competing for the same space. Backside power delivery splits those two jobs: power moves to the back, signals stay on the front. Physics first: a transistor needs a clean, low-resistance path to its supply voltage, and putting that path on the back shortens it and removes it from the crowded front-side metal.

The clearest way to see what the technique covers is to read a granted patent rather than a roadmap slide. Intel Corporation's U.S. Patent No. 12,051,692 B2, titled “Integrated circuit structure with front side signal lines and backside power delivery,” describes exactly this division of labor in its claim language: signal lines on the front side of the device structure, and a power-delivery network reaching the transistors from the back. The title alone, drawn from the granted claims, names the two halves of the architecture and the boundary between them.

"Integrated circuit structure with front side signal lines and backside power delivery"— USPTO, U.S. Patent No. 12,051,692 B2 (title), source

The granted record is not limited to one assignee. Adeia Semiconductor Bonding Technologies holds a family of filings around the same concept, including U.S. publication US20250006632A1, “Embedded chiplets with backside power delivery network,” which carries a priority date of June 30, 2023, and European applications EP4627627A1 and EP4666322A1 covering a backside power delivery network and an interposer for one. Reading those titles together shows the technique being claimed at two levels: inside the transistor stack itself, and at the packaging level where chiplets and interposers connect. Announced is not the same as shipping, but the existence of granted U.S. claims and a multi-assignee filing cluster establishes that backside power delivery is a defined, prosecuted construction rather than a marketing label.

Why the front-side congestion matters

The reason this architecture appears across multiple portfolios traces to a physical constraint. As logic nodes scale, the number of metal layers on the front side grows, and the power rails — which must be wide enough to carry current without excessive voltage drop — take space that the signal routing also wants. The patent record frames backside power delivery as a way to relieve that contention: by moving the power network to the back of the wafer, the front-side layers are freed to route signals, and the power path to the transistor can be made shorter and lower in resistance. That is a structural claim about wiring topology, stated in the device claims, not a performance promise about a particular product.

This is also where the architecture intersects with the rest of the leading-edge story. Backside power delivery is one of the changes that accompanies the move to gate-all-around transistor structures at the most advanced nodes, because both are responses to the same scaling pressure — the transistor is getting smaller and the wiring around it has to be reorganized to keep up. The two technologies are claimed separately in the patent record, but they appear in the same generation of process announcements. A reader tracking node roadmaps should treat backside power delivery as a wiring-architecture change, distinct from the transistor-channel change that gate-all-around represents.

Where the IP cluster points

It is worth reading the assignee spread, because it says something the individual claims do not. Backside power delivery appears in the granted U.S. portfolio of a leading-edge logic maker (Intel's 12,051,692 B2) and, separately, across a bonding-technology specialist's filings (Adeia's US20250006632A1 and the European EP4627627A1 and EP4666322A1). Those are two different vantage points on the same architecture: one from the transistor and front-end side, where the power network is integrated into the device stack, and one from the bonding and packaging side, where backside power is realized through wafer-bonding and interposer techniques. The priority dates run from late 2021 through mid-2023, placing the filing activity squarely in the window when the move to backside power was being designed into the next process generations. None of this is a claim about who will ship first or best — the patent record does not adjudicate that. What it documents is that backside power delivery is being prosecuted from multiple technical directions at once, which is the pattern that tends to surround an architecture the industry treats as a real transition rather than a one-vendor experiment. For a reader, the practical takeaway is to separate the front-end device claim from the packaging-level claim: they describe the same goal — power from the back — reached through different process routes.

What the record shows

The verifiable facts are these. Granted U.S. claims (Intel's 12,051,692 B2) describe an integrated-circuit structure that places signal lines on the front side and a power-delivery network on the back. Additional filings from Adeia (US20250006632A1, priority June 30, 2023; EP4627627A1; EP4666322A1) extend the concept to embedded chiplets and interposers. The patents describe the structural arrangement — power on the back, signal on the front, with connections passing through the substrate — and the stated motivation is to separate power delivery from signal routing so each has its own dedicated wiring real estate. None of that requires reading a vendor roadmap; it is in the prosecuted claim language. What the record does not establish, and what no patent can, is which products ship the architecture in volume or what yield it achieves — those are questions for the foundries' filings, not the patent grants. For the definition itself, the grant is the authority: backside power delivery is the relocation of the power-delivery network to the wafer's back side, claimed as such.