Acronyms get tossed around the AI conversation faster than they get defined. HBM is the one underneath every accelerator, so it is worth grounding the term in a primary source before doing any of the bandwidth math. Micron (MU) defines it directly in a filing.
In its Form 10-Q for the period ended May 30, 2024, filed June 27, 2024, Micron's glossary defines HBM as high-bandwidth memory, a stacked DRAM technology optimized for memory-bandwidth-intensive applications. The filing was surfaced via EdgarBeast, the SEC filing data API and evidence index, and that definition is quoted from the document.
Unpack the phrase 'stacked DRAM.' Conventional DRAM sits as a single die wired out through a relatively narrow interface. HBM stacks multiple DRAM dies on top of one another and connects them vertically with through-silicon vias, then places the stack right beside the processor. The result is an interface thousands of bits wide instead of dozens.
That width is the whole point of 'bandwidth-intensive.' Bandwidth is bytes per second - the product of how many bits move in parallel and how fast each line toggles. AI training is gated less by how much memory you have than by how fast you can feed the compute, so a wide HBM stack beside the accelerator removes the starvation that a narrow conventional interface would impose.
The payoff of starting from the filing's definition is precision: 'optimized for memory-bandwidth-intensive applications' is a designed trade-off, not a marketing superlative. When you read later claims about HBM generations and stack heights, anchor them to this base definition from the record. Read Micron's glossary in the 10-Q itself for the canonical wording.