High-bandwidth memory (HBM) is a form of DRAM in which several memory dies are stacked one atop another and wired to the processor through an unusually wide data interface. The point of the architecture is throughput per unit area: instead of placing flat memory chips around a processor and connecting them over relatively narrow buses, HBM puts a tall stack of DRAM very close to the compute die and gives it thousands of connections, so an enormous number of bytes per second moves over a short distance. That matters because a modern AI accelerator can process data faster than ordinary memory can supply it — the “memory bottleneck” — and HBM exists to keep the processor fed.

The U.S. government's own description of why HBM matters is unusually direct, because it appears in the rule that placed HBM under export control. In the December 5, 2024 interim final rule “Foreign-Produced Direct Product Rule Additions, and Refinements to Controls for Advanced Computing and Semiconductor Manufacturing Items” (89 FR 96790), the Bureau of Industry and Security (BIS) explains the dependency before imposing the control.

"HBM is critical to both AI training and inference at scale and a key component of advanced computing ICs."— Bureau of Industry and Security, 89 FR 96790 (Dec. 5, 2024), source

The bandwidth-density line

What makes the HBM control technically notable is the metric BIS chose to define it. Rather than control HBM on raw bandwidth — total bytes per second per stack — the rule adds a new control on HBM stacks to ECCN 3A090.c keyed to memory bandwidth density, with a threshold expressed in the rule text as 3 GB/s/mm². The agency states the reasoning plainly: HBM units are optimized for very high memory bandwidth, unlike general consumer-grade DRAM, so a density threshold “will narrowly target controls at HBM” and avoid sweeping in ordinary memory. BIS also notes it used bandwidth density rather than total bandwidth so that the control still applies if a design uses a larger quantity of smaller HBM chips to reach the same effective performance — closing an obvious workaround. The metric is bandwidth divided by area: how many gigabytes per second the memory delivers for each square millimeter it occupies.

This is the kind of regulatory engineering that rewards reading the rule rather than the headline. A coverage line that said simply “HBM is now controlled” would miss the load-bearing detail: the control attaches at 3 GB/s/mm², and it is structured around density precisely to remain robust against a chip-count substitution. For anyone tracking how export controls reshape the memory market, that density threshold — not a brand or a generation name — is the actual boundary, and it sits in the Commerce Control List entry, not in a press release.

Why density, not a generation label

HBM is sold in successive generations, each with higher per-stack bandwidth and more dies in the stack. A control written against a generation name would age out the moment a new one shipped. By controlling against bandwidth density, BIS anchored the rule to a physical performance characteristic that tracks the technology forward rather than naming any particular product. The same rule revised the definition of an “advanced-node integrated circuit” as it applies to DRAM, tightening the surrounding framework. The throughline is that the U.S. framed its memory controls in terms of measurable performance — bandwidth per area — because that is what makes HBM strategically valuable to AI compute in the first place.

How the architecture earns the bandwidth

The density metric also maps cleanly onto the physical reason HBM exists, which is worth walking through because it explains why the control targets HBM and not ordinary DRAM. Conventional DRAM is placed flat on a board and connected to the processor over a comparatively narrow bus running a relatively long distance; bandwidth is limited by how many wires can be routed and how fast each can be driven over that distance. HBM inverts the geometry. By stacking the DRAM dies vertically and placing the stack immediately beside the compute die — typically on a shared interposer — the interface can be made enormously wide, with thousands of connections running a very short distance. Bandwidth is roughly the product of interface width and per-pin speed, so a very wide, very short interface delivers far more bytes per second than a flat array of the same total capacity. Crucially, because the stack occupies a small footprint, that bandwidth is concentrated in a small area — which is exactly the quantity the BIS rule measures as bandwidth density. The agency's choice of metric is therefore not arbitrary regulatory math; it tracks the physical property that distinguishes HBM from “general consumer-grade dynamic random access memory,” in the rule's own words. That alignment between the control parameter and the technology's defining trait is why the threshold can “narrowly target controls at HBM” without sweeping in commodity memory.

What the record shows

The verifiable facts: HBM is vertically stacked DRAM connected over a wide interface to deliver high bandwidth in a small footprint, and the U.S. government, in 89 FR 96790 (Dec. 5, 2024), states it is “critical to both AI training and inference at scale.” That same rule added HBM stacks to ECCN 3A090.c using a memory-bandwidth-density threshold of 3 GB/s/mm², chosen so the control narrowly targets HBM and remains effective if smaller HBM chips are used in greater numbers. The rule does not name specific suppliers in defining the technology; it controls a performance characteristic. For the definition and the control line alike, the Federal Register document is the authority. The strategic significance — that the memory feeding AI accelerators is now a controlled item drawn at a specific bandwidth density — is established by the rule's own text, and any number quoted here can be traced to it.