HBM coverage fixates on bandwidth - the terabytes per second a stack can move. But for many workloads the binding constraint is capacity: can the stack hold the working set at all? Xilinx's 2021 grant attacks that second axis with a multi-rank organization.
The grant US11189338B1 (issued November 30, 2021; XILINX, INC.; CPC G11C 11/4096 DRAM array access, H01L 23/538 interconnect substrate, H01L 25/18 multi-chip assembly) claims multi-rank HBM. The G11C 11/4096 code points at how the array is accessed; the H01L 25/18 code anchors it in real stacked-die packaging.
What does multi-rank buy you? Think of ranks as parallel groups of memory the controller can select between. By organizing the HBM into multiple ranks, you can grow total capacity and improve how concurrent accesses are scheduled without simply widening the already-wide interface - a different knob than raw bandwidth.
The assignee matters for the competitive read. Xilinx, an FPGA maker later acquired by AMD, sat at the intersection of memory-hungry reconfigurable logic and HBM - exactly the kind of customer that needed both bandwidth and capacity. Filing multi-rank HBM IP in 2021 protected that position.
Bandwidth and capacity trade against each other in real designs, and the patent record reflects engineers working both. A stack tuned only for GB/s may starve a workload that needs gigabytes; multi-rank organization is one way to bend the capacity curve up while keeping the high-bandwidth interface.
The reader's takeaway: when an HBM datasheet quotes bandwidth, ask about ranks and capacity too. Xilinx's 2021 grant is a claim on the capacity dimension, and capacity is frequently the constraint that actually decides whether a model or a netlist fits in fast memory.